From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bmeng@tinylab.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v3 36/43] hw/intc: sifive_plic: Update "num-sources" property default value
Date: Fri, 6 Jan 2023 13:13:50 +1000 [thread overview]
Message-ID: <20230106031357.777790-37-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com>
From: Bin Meng <bmeng@tinylab.org>
At present the default value of "num-sources" property is zero,
which does not make a lot of sense, as in sifive_plic_realize()
we see s->bitfield_words is calculated by:
s->bitfield_words = (s->num_sources + 31) >> 5;
if the we don't configure "num-sources" property its default value
zero makes s->bitfield_words zero too, which isn't true because
interrupt source 0 still occupies one word.
Let's change the default value to 1 meaning that only interrupt
source 0 is supported by default and a sanity check in realize().
While we are here, add a comment to describe the exact meaning of
this property that the number should include interrupt source 0.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-9-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9cb4c6d6d4..1edeb1e1ed 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
parse_hart_config(s);
+ if (!s->num_sources) {
+ error_setg(errp, "plic: invalid number of interrupt sources");
+ return;
+ }
+
s->bitfield_words = (s->num_sources + 31) >> 5;
s->num_enables = s->bitfield_words * s->num_addrs;
s->source_priority = g_new0(uint32_t, s->num_sources);
@@ -420,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = {
static Property sifive_plic_properties[] = {
DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
- DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+ /* number of interrupt sources including interrupt source 0 */
+ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
--
2.39.0
next prev parent reply other threads:[~2023-01-06 3:23 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 3:13 [PULL v3 00/43] riscv-to-apply queue Alistair Francis
2023-01-06 3:13 ` [PULL v3 01/43] target/riscv: Fix PMP propagation for tlb Alistair Francis
2023-01-06 3:13 ` [PULL v3 02/43] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2023-01-06 3:13 ` [PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2023-01-06 3:13 ` [PULL v3 04/43] tcg/riscv: Fix base register for user-only qemu_ld/st Alistair Francis
2023-01-06 3:13 ` [PULL v3 05/43] hw/riscv/opentitan: bump opentitan Alistair Francis
2023-01-06 3:13 ` [PULL v3 06/43] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2023-01-06 3:13 ` [PULL v3 07/43] target/riscv: Add smstateen support Alistair Francis
2023-01-06 3:13 ` [PULL v3 08/43] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2023-01-06 3:13 ` [PULL v3 09/43] target/riscv: generate virtual instruction exception Alistair Francis
2023-01-06 3:13 ` [PULL v3 10/43] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2023-01-06 3:13 ` [PULL v3 11/43] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2023-01-06 3:13 ` [PULL v3 12/43] target/riscv: Enable native debug itrigger Alistair Francis
2023-01-06 3:13 ` [PULL v3 13/43] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2023-01-06 3:13 ` [PULL v3 14/43] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2023-01-06 3:13 ` [PULL v3 15/43] target/riscv: Typo fix in sstc() predicate Alistair Francis
2023-01-06 3:13 ` [PULL v3 16/43] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2023-01-06 3:13 ` [PULL v3 17/43] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2023-01-06 3:13 ` [PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2023-01-06 3:13 ` [PULL v3 19/43] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2023-01-06 3:13 ` [PULL v3 20/43] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2023-01-06 3:13 ` [PULL v3 21/43] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2023-01-06 3:13 ` [PULL v3 22/43] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2023-01-06 3:13 ` [PULL v3 23/43] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2023-01-06 3:13 ` [PULL v3 24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2023-01-06 3:13 ` [PULL v3 25/43] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2023-01-06 3:13 ` [PULL v3 26/43] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2023-01-06 3:13 ` [PULL v3 27/43] RISC-V: Add Zawrs ISA extension support Alistair Francis
2023-01-06 3:13 ` [PULL v3 28/43] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 29/43] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2023-01-06 3:13 ` [PULL v3 30/43] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 31/43] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2023-01-06 3:13 ` [PULL v3 32/43] hw/riscv: spike: Remove misleading comments Alistair Francis
2023-01-06 3:13 ` [PULL v3 33/43] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2023-01-06 3:13 ` [PULL v3 34/43] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2023-01-06 3:13 ` [PULL v3 35/43] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2023-01-06 3:13 ` Alistair Francis [this message]
2023-01-06 3:13 ` [PULL v3 37/43] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 38/43] hw/riscv: sifive_e: " Alistair Francis
2023-01-06 3:13 ` [PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2023-01-06 3:13 ` [PULL v3 40/43] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2023-01-06 3:13 ` [PULL v3 41/43] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2023-01-06 3:13 ` [PULL v3 42/43] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2023-01-06 3:13 ` [PULL v3 43/43] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2023-01-07 13:07 ` [PULL v3 00/43] riscv-to-apply queue Peter Maydell
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