From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v3 04/43] tcg/riscv: Fix base register for user-only qemu_ld/st
Date: Fri, 6 Jan 2023 13:13:18 +1000 [thread overview]
Message-ID: <20230106031357.777790-5-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230106031357.777790-1-alistair.francis@opensource.wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.
Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the register usage clear.
Set base after each step of the address arithmetic instead of before.
Return the base register used from tcg_out_tlb_load, so as to
keep that register choice localized to that function.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 2a84c57bec..e3b608034f 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -923,9 +923,9 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
tcg_debug_assert(ok);
}
-static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
- TCGReg addrh, MemOpIdx oi,
- tcg_insn_unit **label_ptr, bool is_load)
+static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
+ TCGReg addrh, MemOpIdx oi,
+ tcg_insn_unit **label_ptr, bool is_load)
{
MemOp opc = get_memop(oi);
unsigned s_bits = opc & MO_SIZE;
@@ -975,6 +975,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
addrl = TCG_REG_TMP0;
}
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
+ return TCG_REG_TMP0;
}
static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
@@ -1177,7 +1178,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#else
unsigned a_bits;
#endif
- TCGReg base = TCG_REG_TMP0;
+ TCGReg base;
data_regl = *args++;
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -1187,23 +1188,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
+ base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
add_qemu_ldst_label(s, 1, oi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, true, addr_regl, a_bits);
}
+ base = addr_regl;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, TCG_REG_TMP0, base);
+ base = TCG_REG_TMP0;
+ }
if (guest_base != 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
+ base = TCG_REG_TMP0;
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@@ -1249,7 +1252,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
#else
unsigned a_bits;
#endif
- TCGReg base = TCG_REG_TMP0;
+ TCGReg base;
data_regl = *args++;
data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
@@ -1259,23 +1262,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
+ base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
add_qemu_ldst_label(s, 0, oi,
(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addr_regl);
- addr_regl = base;
- }
a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, false, addr_regl, a_bits);
}
+ base = addr_regl;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, TCG_REG_TMP0, base);
+ base = TCG_REG_TMP0;
+ }
if (guest_base != 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
+ base = TCG_REG_TMP0;
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
--
2.39.0
next prev parent reply other threads:[~2023-01-06 3:33 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 3:13 [PULL v3 00/43] riscv-to-apply queue Alistair Francis
2023-01-06 3:13 ` [PULL v3 01/43] target/riscv: Fix PMP propagation for tlb Alistair Francis
2023-01-06 3:13 ` [PULL v3 02/43] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Alistair Francis
2023-01-06 3:13 ` [PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Alistair Francis
2023-01-06 3:13 ` Alistair Francis [this message]
2023-01-06 3:13 ` [PULL v3 05/43] hw/riscv/opentitan: bump opentitan Alistair Francis
2023-01-06 3:13 ` [PULL v3 06/43] hw/riscv/opentitan: add aon_timer base unimpl Alistair Francis
2023-01-06 3:13 ` [PULL v3 07/43] target/riscv: Add smstateen support Alistair Francis
2023-01-06 3:13 ` [PULL v3 08/43] target/riscv: smstateen check for h/s/envcfg Alistair Francis
2023-01-06 3:13 ` [PULL v3 09/43] target/riscv: generate virtual instruction exception Alistair Francis
2023-01-06 3:13 ` [PULL v3 10/43] target/riscv: Add itrigger support when icount is not enabled Alistair Francis
2023-01-06 3:13 ` [PULL v3 11/43] target/riscv: Add itrigger support when icount is enabled Alistair Francis
2023-01-06 3:13 ` [PULL v3 12/43] target/riscv: Enable native debug itrigger Alistair Francis
2023-01-06 3:13 ` [PULL v3 13/43] target/riscv: Add itrigger_enabled field to CPURISCVState Alistair Francis
2023-01-06 3:13 ` [PULL v3 14/43] hw/intc: sifive_plic: Renumber the S irqs for numa support Alistair Francis
2023-01-06 3:13 ` [PULL v3 15/43] target/riscv: Typo fix in sstc() predicate Alistair Francis
2023-01-06 3:13 ` [PULL v3 16/43] hw/riscv: virt: Remove the redundant ipi-id property Alistair Francis
2023-01-06 3:13 ` [PULL v3 17/43] target/riscv: support cache-related PMU events in virtual mode Alistair Francis
2023-01-06 3:13 ` [PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() Alistair Francis
2023-01-06 3:13 ` [PULL v3 19/43] hw/misc: pfsoc: add fabric clocks to ioscb Alistair Francis
2023-01-06 3:13 ` [PULL v3 20/43] hw/riscv: pfsoc: add missing FICs as unimplemented Alistair Francis
2023-01-06 3:13 ` [PULL v3 21/43] hw/{misc, riscv}: pfsoc: add system controller " Alistair Francis
2023-01-06 3:13 ` [PULL v3 22/43] hw/intc: sifive_plic: fix out-of-bound access of source_priority array Alistair Francis
2023-01-06 3:13 ` [PULL v3 23/43] target/riscv: Fix mret exception cause when no pmp rule is configured Alistair Francis
2023-01-06 3:13 ` [PULL v3 24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn Alistair Francis
2023-01-06 3:13 ` [PULL v3 25/43] target/riscv: Simplify helper_sret() a little bit Alistair Francis
2023-01-06 3:13 ` [PULL v3 26/43] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ Alistair Francis
2023-01-06 3:13 ` [PULL v3 27/43] RISC-V: Add Zawrs ISA extension support Alistair Francis
2023-01-06 3:13 ` [PULL v3 28/43] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 29/43] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Alistair Francis
2023-01-06 3:13 ` [PULL v3 30/43] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 31/43] hw/riscv: Sort machines Kconfig options in alphabetical order Alistair Francis
2023-01-06 3:13 ` [PULL v3 32/43] hw/riscv: spike: Remove misleading comments Alistair Francis
2023-01-06 3:13 ` [PULL v3 33/43] hw/intc: sifive_plic: Drop PLICMode_H Alistair Francis
2023-01-06 3:13 ` [PULL v3 34/43] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Alistair Francis
2023-01-06 3:13 ` [PULL v3 35/43] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() Alistair Francis
2023-01-06 3:13 ` [PULL v3 36/43] hw/intc: sifive_plic: Update "num-sources" property default value Alistair Francis
2023-01-06 3:13 ` [PULL v3 37/43] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Alistair Francis
2023-01-06 3:13 ` [PULL v3 38/43] hw/riscv: sifive_e: " Alistair Francis
2023-01-06 3:13 ` [PULL v3 39/43] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Alistair Francis
2023-01-06 3:13 ` [PULL v3 40/43] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Alistair Francis
2023-01-06 3:13 ` [PULL v3 41/43] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Alistair Francis
2023-01-06 3:13 ` [PULL v3 42/43] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Alistair Francis
2023-01-06 3:13 ` [PULL v3 43/43] hw/intc: sifive_plic: Fix the pending register range check Alistair Francis
2023-01-07 13:07 ` [PULL v3 00/43] riscv-to-apply queue Peter Maydell
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