From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org,
qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net
Subject: [PATCH v4 32/36] target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG
Date: Sat, 7 Jan 2023 18:37:15 -0800 [thread overview]
Message-ID: <20230108023719.2466341-33-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/helper.h | 2 --
target/s390x/tcg/insn-data.h.inc | 2 +-
target/s390x/tcg/mem_helper.c | 52 ---------------------------
target/s390x/tcg/translate.c | 60 ++++++++++++++++++++------------
4 files changed, 38 insertions(+), 78 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index bccd3bfca6..341bc51ec2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32)
DEF_HELPER_3(celgb, i64, env, i64, i32)
DEF_HELPER_3(cdlgb, i64, env, i64, i32)
DEF_HELPER_3(cxlgb, i128, env, i64, i32)
-DEF_HELPER_4(cdsg, void, env, i64, i32, i32)
-DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32)
DEF_HELPER_4(csst, i32, env, i32, i64, i64)
DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64)
DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 893f4b48db..ea34b4a277 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -276,7 +276,7 @@
/* COMPARE DOUBLE AND SWAP */
D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ)
- C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0)
+ C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, r1_D64, r1_D64, cdsg, 0)
/* COMPARE AND SWAP AND STORE */
C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 49969abda7..d6725fd18c 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
return cc;
}
-void HELPER(cdsg)(CPUS390XState *env, uint64_t addr,
- uint32_t r1, uint32_t r3)
-{
- uintptr_t ra = GETPC();
- Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
- Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
- Int128 oldv;
- uint64_t oldh, oldl;
- bool fail;
-
- check_alignment(env, addr, 16, ra);
-
- oldh = cpu_ldq_data_ra(env, addr + 0, ra);
- oldl = cpu_ldq_data_ra(env, addr + 8, ra);
-
- oldv = int128_make128(oldl, oldh);
- fail = !int128_eq(oldv, cmpv);
- if (fail) {
- newv = oldv;
- }
-
- cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra);
- cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra);
-
- env->cc_op = fail;
- env->regs[r1] = int128_gethi(oldv);
- env->regs[r1 + 1] = int128_getlo(oldv);
-}
-
-void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
- uint32_t r1, uint32_t r3)
-{
- uintptr_t ra = GETPC();
- Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
- Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
- int mem_idx;
- MemOpIdx oi;
- Int128 oldv;
- bool fail;
-
- assert(HAVE_CMPXCHG128);
-
- mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
- oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
- fail = !int128_eq(oldv, cmpv);
-
- env->cc_op = fail;
- env->regs[r1] = int128_gethi(oldv);
- env->regs[r1 + 1] = int128_getlo(oldv);
-}
-
static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
uint64_t a2, bool parallel)
{
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index d422a1e62b..0dafa27dab 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -2224,31 +2224,22 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s, r1);
- int r3 = get_field(s, r3);
- int d2 = get_field(s, d2);
- int b2 = get_field(s, b2);
- DisasJumpType ret = DISAS_NEXT;
- TCGv_i64 addr;
- TCGv_i32 t_r1, t_r3;
- /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */
- addr = get_address(s, 0, b2, d2);
- t_r1 = tcg_const_i32(r1);
- t_r3 = tcg_const_i32(r3);
- if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
- gen_helper_cdsg(cpu_env, addr, t_r1, t_r3);
- } else if (HAVE_CMPXCHG128) {
- gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3);
- } else {
- gen_helper_exit_atomic(cpu_env);
- ret = DISAS_NORETURN;
- }
- tcg_temp_free_i64(addr);
- tcg_temp_free_i32(t_r1);
- tcg_temp_free_i32(t_r3);
+ /* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */
+ tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_128,
+ get_mem_index(s), MO_BE | MO_128 | MO_ALIGN);
- set_cc_static(s);
- return ret;
+ /*
+ * Extract result into cc_dst:cc_src, compare vs the expected value
+ * in the as yet unmodified input registers, then update CC_OP.
+ */
+ tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128);
+ tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]);
+ tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]);
+ tcg_gen_or_i64(cc_dst, cc_dst, cc_src);
+ set_cc_nz_u64(s, cc_dst);
+
+ return DISAS_NEXT;
}
static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
@@ -5419,6 +5410,14 @@ static void prep_r1_P(DisasContext *s, DisasOps *o)
}
#define SPEC_prep_r1_P SPEC_r1_even
+static void prep_r1_D64(DisasContext *s, DisasOps *o)
+{
+ int r1 = get_field(s, r1);
+ o->out_128 = tcg_temp_new_i128();
+ tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]);
+}
+#define SPEC_prep_r1_D64 SPEC_r1_even
+
static void prep_x1(DisasContext *s, DisasOps *o)
{
o->out_128 = load_freg_128(get_field(s, r1));
@@ -5488,6 +5487,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o)
}
#define SPEC_wout_r1_D32 SPEC_r1_even
+static void wout_r1_D64(DisasContext *s, DisasOps *o)
+{
+ int r1 = get_field(s, r1);
+ tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128);
+}
+#define SPEC_wout_r1_D64 SPEC_r1_even
+
static void wout_r3_P32(DisasContext *s, DisasOps *o)
{
int r3 = get_field(s, r3);
@@ -5935,6 +5941,14 @@ static void in2_r3(DisasContext *s, DisasOps *o)
}
#define SPEC_in2_r3 0
+static void in2_r3_D64(DisasContext *s, DisasOps *o)
+{
+ int r3 = get_field(s, r3);
+ o->in2_128 = tcg_temp_new_i128();
+ tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]);
+}
+#define SPEC_in2_r3_D64 SPEC_r3_even
+
static void in2_r3_sr32(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
--
2.34.1
next prev parent reply other threads:[~2023-01-08 2:51 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-08 2:36 [PATCH v4 00/36] tcg: Support for Int128 with helpers Richard Henderson
2023-01-08 2:36 ` [PATCH v4 01/36] tcg: Define TCG_TYPE_I128 and related helper macros Richard Henderson
2023-01-10 23:27 ` Alex Bennée
2023-01-24 23:44 ` Philippe Mathieu-Daudé
2023-01-08 2:36 ` [PATCH v4 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Richard Henderson
2023-01-11 7:59 ` Alex Bennée
2023-01-08 2:36 ` [PATCH v4 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Richard Henderson
2023-01-11 9:59 ` Alex Bennée
2023-01-11 15:06 ` Richard Henderson
2023-01-08 2:36 ` [PATCH v4 04/36] tcg: Introduce tcg_out_addi_ptr Richard Henderson
2023-01-25 8:31 ` Alex Bennée
2023-01-08 2:36 ` [PATCH v4 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Richard Henderson
2023-01-08 2:36 ` [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Richard Henderson
2023-01-25 21:09 ` Alex Bennée
2023-01-26 4:11 ` Richard Henderson
2023-01-08 2:36 ` [PATCH v4 07/36] tcg: Add TCG_CALL_RET_BY_VEC Richard Henderson
2023-01-25 21:13 ` Alex Bennée
2023-01-08 2:36 ` [PATCH v4 08/36] include/qemu/int128: Use Int128 structure for TCI Richard Henderson
2023-01-24 23:59 ` Philippe Mathieu-Daudé
2023-01-08 2:36 ` [PATCH v4 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2023-01-08 2:36 ` [PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering Richard Henderson
2023-01-11 11:37 ` Philippe Mathieu-Daudé
2023-01-08 2:36 ` [PATCH v4 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2023-01-08 2:36 ` [PATCH v4 12/36] tcg: " Richard Henderson
2023-01-08 2:36 ` [PATCH v4 13/36] tcg: Add temp allocation for TCGv_i128 Richard Henderson
2023-01-25 0:13 ` Philippe Mathieu-Daudé
2023-01-08 2:36 ` [PATCH v4 14/36] tcg: Add basic data movement " Richard Henderson
2023-01-11 11:41 ` Philippe Mathieu-Daudé
2023-01-08 2:36 ` [PATCH v4 15/36] tcg: Add guest load/store primitives " Richard Henderson
2023-01-08 2:36 ` [PATCH v4 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Richard Henderson
2023-01-08 2:37 ` [PATCH v4 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Richard Henderson
2023-01-08 2:37 ` [PATCH v4 18/36] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP Richard Henderson
2023-01-08 2:37 ` [PATCH v4 19/36] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP Richard Henderson
2023-01-08 2:37 ` [PATCH v4 20/36] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX Richard Henderson
2023-01-08 2:37 ` [PATCH v4 21/36] tests/tcg/s390x: Add div.c Richard Henderson
2023-01-08 2:37 ` [PATCH v4 22/36] tests/tcg/s390x: Add clst.c Richard Henderson
2023-01-08 2:37 ` [PATCH v4 23/36] tests/tcg/s390x: Add long-double.c Richard Henderson
2023-01-08 2:37 ` [PATCH v4 24/36] target/s390x: Use a single return for helper_divs32/u32 Richard Henderson
2023-01-08 2:37 ` [PATCH v4 25/36] target/s390x: Use a single return for helper_divs64/u64 Richard Henderson
2023-01-08 2:37 ` [PATCH v4 26/36] target/s390x: Use Int128 for return from CLST Richard Henderson
2023-01-08 2:37 ` [PATCH v4 27/36] target/s390x: Use Int128 for return from CKSM Richard Henderson
2023-01-08 2:37 ` [PATCH v4 28/36] target/s390x: Use Int128 for return from TRE Richard Henderson
2023-01-08 2:37 ` [PATCH v4 29/36] target/s390x: Copy wout_x1 to wout_x1_P Richard Henderson
2023-01-08 2:37 ` [PATCH v4 30/36] target/s390x: Use Int128 for returning float128 Richard Henderson
2023-01-08 2:37 ` [PATCH v4 31/36] target/s390x: Use Int128 for passing float128 Richard Henderson
2023-01-08 2:37 ` Richard Henderson [this message]
2023-01-08 2:37 ` [PATCH v4 33/36] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc Richard Henderson
2023-01-08 2:37 ` [PATCH v4 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Richard Henderson
2023-01-25 22:53 ` Philippe Mathieu-Daudé
2023-01-08 2:37 ` [PATCH v4 35/36] target/i386: Inline cmpxchg8b Richard Henderson
2023-01-08 2:37 ` [PATCH v4 36/36] target/i386: Inline cmpxchg16b Richard Henderson
2023-01-10 23:12 ` [PATCH v4 00/36] tcg: Support for Int128 with helpers Mark Cave-Ayland
2023-01-24 21:46 ` Richard Henderson
2023-01-24 21:54 ` Richard Henderson
2023-01-25 21:50 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230108023719.2466341-33-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=eduardo@habkost.net \
--cc=pbonzini@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).