From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "John G Johnson" <john.g.johnson@oracle.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Igor Mammedov" <imammedo@redhat.com>,
"Elena Ufimtseva" <elena.ufimtseva@oracle.com>,
"Ani Sinha" <ani@anisinha.ca>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Jagannathan Raman" <jag.raman@oracle.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"John Snow" <jsnow@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
qemu-ppc@nongnu.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
qemu-block@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
qemu-arm@nongnu.org, "Hervé Poussineau" <hpoussin@reactos.org>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v6 22/33] hw/isa/piix3: Drop the "3" from PIIX base class
Date: Mon, 9 Jan 2023 18:23:35 +0100 [thread overview]
Message-ID: <20230109172347.1830-23-shentey@gmail.com> (raw)
In-Reply-To: <20230109172347.1830-1-shentey@gmail.com>
This commit marks the finalization of the PIIX3 preparations
to be merged with PIIX4. In particular, PIIXState is prepared
to be reused in piix4.c.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-25-shentey@gmail.com>
---
include/hw/southbridge/piix.h | 6 ++--
hw/isa/piix3.c | 60 +++++++++++++++++------------------
2 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index f48cfd7936..907c3568b6 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -72,11 +72,9 @@ struct PIIXState {
bool has_usb;
bool smm_enabled;
};
-typedef struct PIIXState PIIX3State;
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
- TYPE_PIIX3_PCI_DEVICE)
+#define TYPE_PIIX_PCI_DEVICE "pci-piix"
+OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
#define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index d674130fc9..4ce1653406 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -38,7 +38,7 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{
qemu_set_irq(piix3->pic.in_irqs[pic_irq],
!!(piix3->pic_levels &
@@ -46,7 +46,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
(pic_irq * PIIX_NUM_PIRQS))));
}
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
uint64_t mask;
@@ -61,7 +61,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
piix3->pic_levels |= mask * !!level;
}
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
{
int pic_irq;
@@ -77,13 +77,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
static void piix3_set_irq(void *opaque, int pirq, int level)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
piix3_set_irq_level(piix3, pirq, level);
}
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
@@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
}
/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
+static void piix3_update_irq_levels(PIIXState *piix3)
{
PCIBus *bus = pci_get_bus(&piix3->dev);
int pirq;
@@ -114,7 +114,7 @@ static void piix3_write_config(PCIDevice *dev,
{
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
int pic_irq;
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
@@ -147,7 +147,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
static void piix_reset(DeviceState *dev)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */
@@ -188,7 +188,7 @@ static void piix_reset(DeviceState *dev)
static int piix3_post_load(void *opaque, int version_id)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
int pirq;
/*
@@ -211,7 +211,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix3_pre_save(void *opaque)
{
int i;
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
piix3->pci_irq_levels_vmstate[i] =
@@ -223,7 +223,7 @@ static int piix3_pre_save(void *opaque)
static bool piix3_rcr_needed(void *opaque)
{
- PIIX3State *piix3 = opaque;
+ PIIXState *piix3 = opaque;
return (piix3->rcr != 0);
}
@@ -234,7 +234,7 @@ static const VMStateDescription vmstate_piix3_rcr = {
.minimum_version_id = 1,
.needed = piix3_rcr_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINT8(rcr, PIIX3State),
+ VMSTATE_UINT8(rcr, PIIXState),
VMSTATE_END_OF_LIST()
}
};
@@ -246,8 +246,8 @@ static const VMStateDescription vmstate_piix3 = {
.post_load = piix3_post_load,
.pre_save = piix3_pre_save,
.fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX3State),
- VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+ VMSTATE_PCI_DEVICE(dev, PIIXState),
+ VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
PIIX_NUM_PIRQS, 3),
VMSTATE_END_OF_LIST()
},
@@ -260,7 +260,7 @@ static const VMStateDescription vmstate_piix3 = {
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{
- PIIX3State *d = opaque;
+ PIIXState *d = opaque;
if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@@ -271,7 +271,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
{
- PIIX3State *d = opaque;
+ PIIXState *d = opaque;
return d->rcr;
}
@@ -288,7 +288,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PIIXState *d = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
@@ -374,7 +374,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
static void pci_piix3_init(Object *obj)
{
- PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+ PIIXState *d = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
@@ -382,10 +382,10 @@ static void pci_piix3_init(Object *obj)
}
static Property pci_piix_props[] = {
- DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0),
- DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true),
- DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
- DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false),
+ DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
+ DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
+ DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
+ DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -412,10 +412,10 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
adevc->build_dev_aml = build_pci_isa_aml;
}
-static const TypeInfo piix3_pci_type_info = {
- .name = TYPE_PIIX3_PCI_DEVICE,
+static const TypeInfo piix_pci_type_info = {
+ .name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX3State),
+ .instance_size = sizeof(PIIXState),
.instance_init = pci_piix3_init,
.abstract = true,
.class_init = pci_piix3_class_init,
@@ -429,7 +429,7 @@ static const TypeInfo piix3_pci_type_info = {
static void piix3_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp);
@@ -451,14 +451,14 @@ static void piix3_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
+ .parent = TYPE_PIIX_PCI_DEVICE,
.class_init = piix3_class_init,
};
static void piix3_xen_realize(PCIDevice *dev, Error **errp)
{
ERRP_GUARD();
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp);
@@ -485,13 +485,13 @@ static void piix3_xen_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_xen_info = {
.name = TYPE_PIIX3_XEN_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
+ .parent = TYPE_PIIX_PCI_DEVICE,
.class_init = piix3_xen_class_init,
};
static void piix3_register_types(void)
{
- type_register_static(&piix3_pci_type_info);
+ type_register_static(&piix_pci_type_info);
type_register_static(&piix3_info);
type_register_static(&piix3_xen_info);
}
--
2.39.0
next prev parent reply other threads:[~2023-01-09 17:45 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 17:23 [PATCH v6 00/33] Consolidate PIIX south bridges Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 01/33] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 02/33] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 03/33] hw/isa/piix4: Correct IRQRC[A:D] reset values Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 04/33] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() Bernhard Beschow
2023-01-13 10:13 ` Philippe Mathieu-Daudé
2023-01-13 17:37 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 05/33] hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 06/33] hw/isa/piix4: " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 07/33] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 08/33] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 09/33] hw/intc/i8259: Make using the isa_pic singleton more type-safe Bernhard Beschow
2023-01-12 12:40 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 10/33] hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC Bernhard Beschow
2023-01-12 12:40 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 11/33] hw/i386/pc: Create RTC controllers in south bridges Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 12/33] hw/i386/pc: No need for rtc_state to be an out-parameter Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 13/33] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2023-01-12 12:43 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device Bernhard Beschow
2023-01-12 12:45 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 15/33] hw/isa/piix3: Create power management " Bernhard Beschow
2023-01-12 12:46 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 16/33] hw/isa/piix3: Create TYPE_ISA_PIC " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 17/33] hw/isa/piix3: Create IDE controller " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 18/33] hw/isa/piix3: Wire up ACPI interrupt internally Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 19/33] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 20/33] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 21/33] hw/isa/piix3: Rename piix3_reset() " Bernhard Beschow
2023-01-09 17:23 ` Bernhard Beschow [this message]
2023-01-12 12:48 ` [PATCH v6 22/33] hw/isa/piix3: Drop the "3" from PIIX base class Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 23/33] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 24/33] hw/isa/piix4: Remove unused inbound ISA interrupt lines Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 25/33] hw/isa/piix4: Use TYPE_ISA_PIC device Bernhard Beschow
2023-01-11 17:08 ` Philippe Mathieu-Daudé
2023-01-11 22:47 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 26/33] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 27/33] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 28/33] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2023-01-12 12:50 ` Philippe Mathieu-Daudé
2023-01-12 13:32 ` Philippe Mathieu-Daudé
2023-01-12 18:24 ` Bernhard Beschow
2023-01-12 15:04 ` Philippe Mathieu-Daudé
2023-01-12 16:31 ` Philippe Mathieu-Daudé
2023-01-12 18:03 ` Bernhard Beschow
2023-01-12 16:36 ` Philippe Mathieu-Daudé
2023-01-12 18:21 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 29/33] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 30/33] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2023-01-12 12:51 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 31/33] hw/isa/piix: Rename functions to be shared for interrupt triggering Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 32/33] hw/isa/piix: Consolidate IRQ triggering Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 33/33] hw/isa/piix: Share PIIX3's base class with PIIX4 Bernhard Beschow
2023-01-13 8:46 ` [PATCH v6 00/33] Consolidate PIIX south bridges Philippe Mathieu-Daudé
2023-01-13 17:39 ` Bernhard Beschow
2023-01-20 12:22 ` Bernhard Beschow
2023-01-23 9:25 ` Philippe Mathieu-Daudé
2023-01-23 15:51 ` Bernhard Beschow
2023-02-10 16:27 ` Bernhard Beschow
2023-02-10 17:11 ` Philippe Mathieu-Daudé
2023-02-11 16:23 ` Bernhard Beschow
2023-02-12 12:51 ` Bernhard Beschow
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