From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "John G Johnson" <john.g.johnson@oracle.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Igor Mammedov" <imammedo@redhat.com>,
"Elena Ufimtseva" <elena.ufimtseva@oracle.com>,
"Ani Sinha" <ani@anisinha.ca>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Jagannathan Raman" <jag.raman@oracle.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"John Snow" <jsnow@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
qemu-ppc@nongnu.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
qemu-block@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
qemu-arm@nongnu.org, "Hervé Poussineau" <hpoussin@reactos.org>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v6 33/33] hw/isa/piix: Share PIIX3's base class with PIIX4
Date: Mon, 9 Jan 2023 18:23:46 +0100 [thread overview]
Message-ID: <20230109172347.1830-34-shentey@gmail.com> (raw)
In-Reply-To: <20230109172347.1830-1-shentey@gmail.com>
Having a common base class will allow for substituting PIIX3 with PIIX4
and vice versa. Moreover, it makes PIIX4 implement the
acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-42-shentey@gmail.com>
---
hw/isa/piix.c | 49 ++++++++++++++++++++++---------------------------
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index f125a6175f..54a1246a9d 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -396,13 +396,12 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
}
}
-static void pci_piix3_init(Object *obj)
+static void pci_piix_init(Object *obj)
{
PIIXState *d = PIIX_PCI_DEVICE(obj);
object_initialize_child(obj, "pic", &d->pic, TYPE_ISA_PIC);
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
- object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
static Property pci_piix_props[] = {
@@ -413,7 +412,7 @@ static Property pci_piix_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
+static void pci_piix_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -421,11 +420,8 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
dc->reset = piix_reset;
dc->desc = "ISA bridge";
- dc->vmsd = &vmstate_piix3;
dc->hotpluggable = false;
k->vendor_id = PCI_VENDOR_ID_INTEL;
- /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
- k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
k->class_id = PCI_CLASS_BRIDGE_ISA;
/*
* Reason: part of PIIX3 southbridge, needs to be wired up by
@@ -440,9 +436,9 @@ static const TypeInfo piix_pci_type_info = {
.name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIXState),
- .instance_init = pci_piix3_init,
+ .instance_init = pci_piix_init,
.abstract = true,
- .class_init = pci_piix3_class_init,
+ .class_init = pci_piix_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ TYPE_ACPI_DEV_AML_IF },
@@ -465,17 +461,29 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
}
+static void piix3_init(Object *obj)
+{
+ PIIXState *d = PIIX_PCI_DEVICE(obj);
+
+ object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
+}
+
static void piix3_class_init(ObjectClass *klass, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix_write_config;
k->realize = piix3_realize;
+ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+ dc->vmsd = &vmstate_piix3;
}
static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE,
.parent = TYPE_PIIX_PCI_DEVICE,
+ .instance_init = piix3_init,
.class_init = piix3_class_init,
};
@@ -501,15 +509,20 @@ static void piix3_xen_realize(PCIDevice *dev, Error **errp)
static void piix3_xen_class_init(ObjectClass *klass, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->config_write = piix3_write_config_xen;
k->realize = piix3_xen_realize;
+ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+ dc->vmsd = &vmstate_piix3;
}
static const TypeInfo piix3_xen_info = {
.name = TYPE_PIIX3_XEN_DEVICE,
.parent = TYPE_PIIX_PCI_DEVICE,
+ .instance_init = piix3_init,
.class_init = piix3_xen_class_init,
};
@@ -540,8 +553,6 @@ static void piix4_init(Object *obj)
{
PIIXState *s = PIIX_PCI_DEVICE(obj);
- object_initialize_child(obj, "pic", &s->pic, TYPE_ISA_PIC);
- object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
}
@@ -552,31 +563,15 @@ static void piix4_class_init(ObjectClass *klass, void *data)
k->config_write = piix_write_config;
k->realize = piix4_realize;
- k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
- k->class_id = PCI_CLASS_BRIDGE_ISA;
- dc->reset = piix_reset;
- dc->desc = "ISA bridge";
dc->vmsd = &vmstate_piix4;
- /*
- * Reason: part of PIIX4 southbridge, needs to be wired up,
- * e.g. by mips_malta_init()
- */
- dc->user_creatable = false;
- dc->hotpluggable = false;
- device_class_set_props(dc, pci_piix_props);
}
static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIXState),
+ .parent = TYPE_PIIX_PCI_DEVICE,
.instance_init = piix4_init,
.class_init = piix4_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
};
static void piix3_register_types(void)
--
2.39.0
next prev parent reply other threads:[~2023-01-09 17:49 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 17:23 [PATCH v6 00/33] Consolidate PIIX south bridges Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 01/33] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 02/33] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 03/33] hw/isa/piix4: Correct IRQRC[A:D] reset values Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 04/33] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() Bernhard Beschow
2023-01-13 10:13 ` Philippe Mathieu-Daudé
2023-01-13 17:37 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 05/33] hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 06/33] hw/isa/piix4: " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 07/33] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 08/33] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 09/33] hw/intc/i8259: Make using the isa_pic singleton more type-safe Bernhard Beschow
2023-01-12 12:40 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 10/33] hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC Bernhard Beschow
2023-01-12 12:40 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 11/33] hw/i386/pc: Create RTC controllers in south bridges Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 12/33] hw/i386/pc: No need for rtc_state to be an out-parameter Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 13/33] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2023-01-12 12:43 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 14/33] hw/isa/piix3: Create USB controller in host device Bernhard Beschow
2023-01-12 12:45 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 15/33] hw/isa/piix3: Create power management " Bernhard Beschow
2023-01-12 12:46 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 16/33] hw/isa/piix3: Create TYPE_ISA_PIC " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 17/33] hw/isa/piix3: Create IDE controller " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 18/33] hw/isa/piix3: Wire up ACPI interrupt internally Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 19/33] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 20/33] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 21/33] hw/isa/piix3: Rename piix3_reset() " Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 22/33] hw/isa/piix3: Drop the "3" from PIIX base class Bernhard Beschow
2023-01-12 12:48 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 23/33] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 24/33] hw/isa/piix4: Remove unused inbound ISA interrupt lines Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 25/33] hw/isa/piix4: Use TYPE_ISA_PIC device Bernhard Beschow
2023-01-11 17:08 ` Philippe Mathieu-Daudé
2023-01-11 22:47 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 26/33] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 27/33] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 28/33] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2023-01-12 12:50 ` Philippe Mathieu-Daudé
2023-01-12 13:32 ` Philippe Mathieu-Daudé
2023-01-12 18:24 ` Bernhard Beschow
2023-01-12 15:04 ` Philippe Mathieu-Daudé
2023-01-12 16:31 ` Philippe Mathieu-Daudé
2023-01-12 18:03 ` Bernhard Beschow
2023-01-12 16:36 ` Philippe Mathieu-Daudé
2023-01-12 18:21 ` Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 29/33] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 30/33] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2023-01-12 12:51 ` Philippe Mathieu-Daudé
2023-01-09 17:23 ` [PATCH v6 31/33] hw/isa/piix: Rename functions to be shared for interrupt triggering Bernhard Beschow
2023-01-09 17:23 ` [PATCH v6 32/33] hw/isa/piix: Consolidate IRQ triggering Bernhard Beschow
2023-01-09 17:23 ` Bernhard Beschow [this message]
2023-01-13 8:46 ` [PATCH v6 00/33] Consolidate PIIX south bridges Philippe Mathieu-Daudé
2023-01-13 17:39 ` Bernhard Beschow
2023-01-20 12:22 ` Bernhard Beschow
2023-01-23 9:25 ` Philippe Mathieu-Daudé
2023-01-23 15:51 ` Bernhard Beschow
2023-02-10 16:27 ` Bernhard Beschow
2023-02-10 17:11 ` Philippe Mathieu-Daudé
2023-02-11 16:23 ` Bernhard Beschow
2023-02-12 12:51 ` Bernhard Beschow
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230109172347.1830-34-shentey@gmail.com \
--to=shentey@gmail.com \
--cc=ani@anisinha.ca \
--cc=aurelien@aurel32.net \
--cc=eduardo@habkost.net \
--cc=elena.ufimtseva@oracle.com \
--cc=f4bug@amsat.org \
--cc=hpoussin@reactos.org \
--cc=imammedo@redhat.com \
--cc=jag.raman@oracle.com \
--cc=jiaxun.yang@flygoat.com \
--cc=john.g.johnson@oracle.com \
--cc=jsnow@redhat.com \
--cc=kraxel@redhat.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).