From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org,
qemu-block@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v2 1/4] hw: Remove hardcoded tabs (code style)
Date: Wed, 11 Jan 2023 09:39:06 +0100 [thread overview]
Message-ID: <20230111083909.42624-2-philmd@linaro.org> (raw)
In-Reply-To: <20230111083909.42624-1-philmd@linaro.org>
We are going to modify this code, fix its style first to avoid
the following checkpatch.pl violations:
ERROR: code indent should never use tabs
ERROR: space prohibited between function name and open parenthesis '('
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/dma/etraxfs_dma.c | 196 +++++++++++++++++++++----------------------
hw/misc/mst_fpga.c | 162 ++++++++++++++++++-----------------
2 files changed, 175 insertions(+), 183 deletions(-)
diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c
index c4334e87bf..88d303ba4a 100644
--- a/hw/dma/etraxfs_dma.c
+++ b/hw/dma/etraxfs_dma.c
@@ -269,34 +269,34 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Load and decode. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Load and decode. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_read(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
- D(dump_d(c, &ctrl->channels[c].current_d));
- ctrl->channels[c].regs[RW_DATA] = addr;
+ D(dump_d(c, &ctrl->channels[c].current_d));
+ ctrl->channels[c].regs[RW_DATA] = addr;
}
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
- D(dump_d(c, &ctrl->channels[c].current_d));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ D(dump_d(c, &ctrl->channels[c].current_d));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_c,
sizeof(ctrl->channels[c].current_c));
}
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
- /* Encode and store. FIXME: handle endianness. */
- D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ /* Encode and store. FIXME: handle endianness. */
+ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
cpu_physical_memory_write(addr, &ctrl->channels[c].current_d,
sizeof(ctrl->channels[c].current_d));
}
@@ -574,46 +574,43 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
static uint32_t dma_rinvalid (void *opaque, hwaddr addr)
{
- hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
- return 0;
+ hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
+ return 0;
}
-static uint64_t
-dma_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size)
{
- struct fs_dma_ctrl *ctrl = opaque;
- int c;
- uint32_t r = 0;
+ struct fs_dma_ctrl *ctrl = opaque;
+ int c;
+ uint32_t r = 0;
- if (size != 4) {
- dma_rinvalid(opaque, addr);
- }
+ if (size != 4) {
+ dma_rinvalid(opaque, addr);
+ }
- /* Make addr relative to this channel and bounded to nr regs. */
- c = fs_channel(addr);
- addr &= 0xff;
- addr >>= 2;
- switch (addr)
- {
- case RW_STAT:
- r = ctrl->channels[c].state & 7;
- r |= ctrl->channels[c].eol << 5;
- r |= ctrl->channels[c].stream_cmd_src << 8;
- break;
+ /* Make addr relative to this channel and bounded to nr regs. */
+ c = fs_channel(addr);
+ addr &= 0xff;
+ addr >>= 2;
+ switch (addr) {
+ case RW_STAT:
+ r = ctrl->channels[c].state & 7;
+ r |= ctrl->channels[c].eol << 5;
+ r |= ctrl->channels[c].stream_cmd_src << 8;
+ break;
- default:
- r = ctrl->channels[c].regs[addr];
- D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
- __func__, c, addr));
- break;
- }
- return r;
+ default:
+ r = ctrl->channels[c].regs[addr];
+ D(printf("%s c=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
+ break;
+ }
+ return r;
}
static void
dma_winvalid (void *opaque, hwaddr addr, uint32_t value)
{
- hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
+ hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
static void
@@ -625,71 +622,68 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
ctrl->channels[c].state = RST;
}
-static void
-dma_write(void *opaque, hwaddr addr,
- uint64_t val64, unsigned int size)
+static void dma_write(void *opaque, hwaddr addr, uint64_t val64,
+ unsigned int size)
{
- struct fs_dma_ctrl *ctrl = opaque;
- uint32_t value = val64;
- int c;
+ struct fs_dma_ctrl *ctrl = opaque;
+ uint32_t value = val64;
+ int c;
- if (size != 4) {
- dma_winvalid(opaque, addr, value);
- }
+ if (size != 4) {
+ dma_winvalid(opaque, addr, value);
+ }
- /* Make addr relative to this channel and bounded to nr regs. */
- c = fs_channel(addr);
- addr &= 0xff;
- addr >>= 2;
- switch (addr)
- {
- case RW_DATA:
- ctrl->channels[c].regs[addr] = value;
- break;
+ /* Make addr relative to this channel and bounded to nr regs. */
+ c = fs_channel(addr);
+ addr &= 0xff;
+ addr >>= 2;
+ switch (addr) {
+ case RW_DATA:
+ ctrl->channels[c].regs[addr] = value;
+ break;
- case RW_CFG:
- ctrl->channels[c].regs[addr] = value;
- dma_update_state(ctrl, c);
- break;
- case RW_CMD:
- /* continue. */
- if (value & ~1)
- printf("Invalid store to ch=%d RW_CMD %x\n",
- c, value);
- ctrl->channels[c].regs[addr] = value;
- channel_continue(ctrl, c);
- break;
-
- case RW_SAVED_DATA:
- case RW_SAVED_DATA_BUF:
- case RW_GROUP:
- case RW_GROUP_DOWN:
- ctrl->channels[c].regs[addr] = value;
- break;
-
- case RW_ACK_INTR:
- case RW_INTR_MASK:
- ctrl->channels[c].regs[addr] = value;
- channel_update_irq(ctrl, c);
- if (addr == RW_ACK_INTR)
- ctrl->channels[c].regs[RW_ACK_INTR] = 0;
- break;
-
- case RW_STREAM_CMD:
- if (value & ~1023)
- printf("Invalid store to ch=%d "
- "RW_STREAMCMD %x\n",
- c, value);
- ctrl->channels[c].regs[addr] = value;
- D(printf("stream_cmd ch=%d\n", c));
- channel_stream_cmd(ctrl, c, value);
- break;
-
- default:
- D(printf ("%s c=%d " TARGET_FMT_plx "\n",
- __func__, c, addr));
- break;
+ case RW_CFG:
+ ctrl->channels[c].regs[addr] = value;
+ dma_update_state(ctrl, c);
+ break;
+ case RW_CMD:
+ /* continue. */
+ if (value & ~1) {
+ printf("Invalid store to ch=%d RW_CMD %x\n", c, value);
}
+ ctrl->channels[c].regs[addr] = value;
+ channel_continue(ctrl, c);
+ break;
+
+ case RW_SAVED_DATA:
+ case RW_SAVED_DATA_BUF:
+ case RW_GROUP:
+ case RW_GROUP_DOWN:
+ ctrl->channels[c].regs[addr] = value;
+ break;
+
+ case RW_ACK_INTR:
+ case RW_INTR_MASK:
+ ctrl->channels[c].regs[addr] = value;
+ channel_update_irq(ctrl, c);
+ if (addr == RW_ACK_INTR) {
+ ctrl->channels[c].regs[RW_ACK_INTR] = 0;
+ }
+ break;
+
+ case RW_STREAM_CMD:
+ if (value & ~1023) {
+ printf("Invalid store to ch=%d RW_STREAMCMD %x\n", c, value);
+ }
+ ctrl->channels[c].regs[addr] = value;
+ D(printf("stream_cmd ch=%d\n", c));
+ channel_stream_cmd(ctrl, c, value);
+ break;
+
+ default:
+ D(printf("%s c=%d " TARGET_FMT_plx "\n", __func__, c, addr));
+ break;
+ }
}
static const MemoryRegionOps dma_ops = {
diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c
index 2aaadfa966..87c09217a6 100644
--- a/hw/misc/mst_fpga.c
+++ b/hw/misc/mst_fpga.c
@@ -99,94 +99,92 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
}
-static uint64_t
-mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
+static uint64_t mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
- mst_irq_state *s = (mst_irq_state *) opaque;
+ mst_irq_state *s = (mst_irq_state *) opaque;
- switch (addr) {
- case MST_LEDDAT1:
- return s->leddat1;
- case MST_LEDDAT2:
- return s->leddat2;
- case MST_LEDCTRL:
- return s->ledctrl;
- case MST_GPSWR:
- return s->gpswr;
- case MST_MSCWR1:
- return s->mscwr1;
- case MST_MSCWR2:
- return s->mscwr2;
- case MST_MSCWR3:
- return s->mscwr3;
- case MST_MSCRD:
- return s->mscrd;
- case MST_INTMSKENA:
- return s->intmskena;
- case MST_INTSETCLR:
- return s->intsetclr;
- case MST_PCMCIA0:
- return s->pcmcia0;
- case MST_PCMCIA1:
- return s->pcmcia1;
- default:
- printf("Mainstone - mst_fpga_readb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
- }
- return 0;
+ switch (addr) {
+ case MST_LEDDAT1:
+ return s->leddat1;
+ case MST_LEDDAT2:
+ return s->leddat2;
+ case MST_LEDCTRL:
+ return s->ledctrl;
+ case MST_GPSWR:
+ return s->gpswr;
+ case MST_MSCWR1:
+ return s->mscwr1;
+ case MST_MSCWR2:
+ return s->mscwr2;
+ case MST_MSCWR3:
+ return s->mscwr3;
+ case MST_MSCRD:
+ return s->mscrd;
+ case MST_INTMSKENA:
+ return s->intmskena;
+ case MST_INTSETCLR:
+ return s->intsetclr;
+ case MST_PCMCIA0:
+ return s->pcmcia0;
+ case MST_PCMCIA1:
+ return s->pcmcia1;
+ default:
+ printf("Mainstone - mst_fpga_readb: Bad register offset "
+ "0x" TARGET_FMT_plx "\n", addr);
+ }
+ return 0;
}
-static void
-mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
+static void mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
{
- mst_irq_state *s = (mst_irq_state *) opaque;
- value &= 0xffffffff;
+ mst_irq_state *s = (mst_irq_state *) opaque;
+ value &= 0xffffffff;
- switch (addr) {
- case MST_LEDDAT1:
- s->leddat1 = value;
- break;
- case MST_LEDDAT2:
- s->leddat2 = value;
- break;
- case MST_LEDCTRL:
- s->ledctrl = value;
- break;
- case MST_GPSWR:
- s->gpswr = value;
- break;
- case MST_MSCWR1:
- s->mscwr1 = value;
- break;
- case MST_MSCWR2:
- s->mscwr2 = value;
- break;
- case MST_MSCWR3:
- s->mscwr3 = value;
- break;
- case MST_MSCRD:
- s->mscrd = value;
- break;
- case MST_INTMSKENA: /* Mask interrupt */
- s->intmskena = (value & 0xFEEFF);
- qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
- break;
- case MST_INTSETCLR: /* clear or set interrupt */
- s->intsetclr = (value & 0xFEEFF);
- qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
- break;
- /* For PCMCIAx allow the to change only power and reset */
- case MST_PCMCIA0:
- s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
- break;
- case MST_PCMCIA1:
- s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
- break;
- default:
- printf("Mainstone - mst_fpga_writeb: Bad register offset "
- "0x" TARGET_FMT_plx "\n", addr);
- }
+ switch (addr) {
+ case MST_LEDDAT1:
+ s->leddat1 = value;
+ break;
+ case MST_LEDDAT2:
+ s->leddat2 = value;
+ break;
+ case MST_LEDCTRL:
+ s->ledctrl = value;
+ break;
+ case MST_GPSWR:
+ s->gpswr = value;
+ break;
+ case MST_MSCWR1:
+ s->mscwr1 = value;
+ break;
+ case MST_MSCWR2:
+ s->mscwr2 = value;
+ break;
+ case MST_MSCWR3:
+ s->mscwr3 = value;
+ break;
+ case MST_MSCRD:
+ s->mscrd = value;
+ break;
+ case MST_INTMSKENA: /* Mask interrupt */
+ s->intmskena = (value & 0xFEEFF);
+ qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
+ break;
+ case MST_INTSETCLR: /* clear or set interrupt */
+ s->intsetclr = (value & 0xFEEFF);
+ qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
+ break;
+ /* For PCMCIAx allow the to change only power and reset */
+ case MST_PCMCIA0:
+ s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
+ break;
+ case MST_PCMCIA1:
+ s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
+ break;
+ default:
+ printf("Mainstone - mst_fpga_writeb: Bad register offset "
+ "0x" TARGET_FMT_plx "\n", addr);
+ }
}
static const MemoryRegionOps mst_fpga_ops = {
--
2.38.1
next prev parent reply other threads:[~2023-01-11 8:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-11 8:39 [PATCH v2 0/4] bulk: Replace TARGET_FMT_plx by HWADDR_PRIx Philippe Mathieu-Daudé
2023-01-11 8:39 ` Philippe Mathieu-Daudé [this message]
2023-01-11 19:48 ` [PATCH v2 1/4] hw: Remove hardcoded tabs (code style) Richard Henderson
2023-01-11 8:39 ` [PATCH v2 2/4] bulk: Coding style fixes Philippe Mathieu-Daudé
2023-01-11 19:48 ` Richard Henderson
2023-01-18 16:09 ` Thomas Huth
2023-01-18 17:04 ` Philippe Mathieu-Daudé
2023-01-11 8:39 ` [PATCH v2 3/4] bulk: Replace TARGET_FMT_plx -> HWADDR_PRIx Philippe Mathieu-Daudé
2023-01-11 19:50 ` Richard Henderson
2023-01-11 8:39 ` [RFC PATCH v2 4/4] bulk: Prefix '0x' to hex values displayed with HWADDR_PRIx format Philippe Mathieu-Daudé
2023-01-20 7:24 ` [PATCH v2 0/4] bulk: Replace TARGET_FMT_plx by HWADDR_PRIx Thomas Huth
2023-01-20 9:59 ` BALATON Zoltan
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