From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Richard Henderson <richard.henderson@linaro.org>
Cc: "Laurent Vivier" <laurent@vivier.eu>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Fabiano Rosas" <farosas@suse.de>,
qemu-arm@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v2 4/7] target/arm/sme: Reset SVE state in aarch64_set_svcr()
Date: Thu, 12 Jan 2023 11:24:33 +0100 [thread overview]
Message-ID: <20230112102436.1913-5-philmd@linaro.org> (raw)
In-Reply-To: <20230112102436.1913-1-philmd@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Move arm_reset_sve_state() calls to aarch64_set_svcr().
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org>
[PMD: Split patch in multiple tiny steps]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
linux-user/aarch64/cpu_loop.c | 1 -
linux-user/aarch64/signal.c | 8 +-------
target/arm/cpu.h | 1 -
target/arm/helper.c | 13 +++++++++++++
target/arm/sme_helper.c | 10 ----------
5 files changed, 14 insertions(+), 19 deletions(-)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index d53742e10b..5e93d27d8f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -96,7 +96,6 @@ void cpu_loop(CPUARMState *env)
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
if (FIELD_EX64(env->svcr, SVCR, SM)) {
arm_rebuild_hflags(env);
- arm_reset_sve_state(env);
}
ret = do_syscall(env,
env->xregs[8],
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index b6e4dcb494..a326a6def5 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -665,14 +665,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
env->btype = 2;
}
- /*
- * Invoke the signal handler with both SM and ZA disabled.
- * When clearing SM, ResetSVEState, per SMSTOP.
- */
+ /* Invoke the signal handler with both SM and ZA disabled. */
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
- if (FIELD_EX64(env->svcr, SVCR, SM)) {
- arm_reset_sve_state(env);
- }
if (env->svcr) {
arm_rebuild_hflags(env);
}
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0484da3322..a471add499 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1124,7 +1124,6 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
-void arm_reset_sve_state(CPUARMState *env);
/*
* SVE registers are encoded in KVM's memory in an endianness-invariant format.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b5626627a1..b655dde27d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6722,11 +6722,24 @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+/* ResetSVEState */
+static void arm_reset_sve_state(CPUARMState *env)
+{
+ memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
+ /* Recall that FFR is stored as pregs[16]. */
+ memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
+ vfp_set_fpcr(env, 0x0800009f);
+}
+
void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
{
uint64_t change = (env->svcr ^ new) & mask;
env->svcr ^= change;
+
+ if (change & R_SVCR_SM_MASK) {
+ arm_reset_sve_state(env);
+ }
}
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 94dc084135..f73bf4d285 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -29,22 +29,12 @@
#include "vec_internal.h"
#include "sve_ldst_internal.h"
-/* ResetSVEState */
-void arm_reset_sve_state(CPUARMState *env)
-{
- memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs));
- /* Recall that FFR is stored as pregs[16]. */
- memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs));
- vfp_set_fpcr(env, 0x0800009f);
-}
-
void helper_set_pstate_sm(CPUARMState *env, uint32_t i)
{
if (i == FIELD_EX64(env->svcr, SVCR, SM)) {
return;
}
aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
- arm_reset_sve_state(env);
arm_rebuild_hflags(env);
}
--
2.38.1
next prev parent reply other threads:[~2023-01-12 10:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 10:24 [PATCH v2 0/7] target/arm: Introduce aarch64_set_svcr Philippe Mathieu-Daudé
2023-01-12 10:24 ` [PATCH v2 1/7] target/arm/sme: Reorg SME access handling in handle_msr_i() Philippe Mathieu-Daudé
2023-01-12 10:24 ` [PATCH v2 2/7] target/arm/sme: Rebuild hflags in set_pstate() helpers Philippe Mathieu-Daudé
2023-01-12 10:24 ` [PATCH v2 3/7] target/arm/sme: Introduce aarch64_set_svcr() Philippe Mathieu-Daudé
2023-01-12 10:24 ` Philippe Mathieu-Daudé [this message]
2023-01-12 10:24 ` [PATCH v2 5/7] target/arm/sme: Reset ZA state in aarch64_set_svcr() Philippe Mathieu-Daudé
2023-01-12 10:24 ` [PATCH v2 6/7] target/arm/sme: Rebuild hflags " Philippe Mathieu-Daudé
2023-01-12 10:24 ` [PATCH v2 7/7] target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr() Philippe Mathieu-Daudé
2023-01-12 14:20 ` [PATCH v2 0/7] target/arm: Introduce aarch64_set_svcr Fabiano Rosas
2023-01-17 16:33 ` Peter Maydell
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