From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng@tinylab.org>
Subject: [PULL 10/37] hw/riscv/boot.c: introduce riscv_default_firmware_name()
Date: Fri, 20 Jan 2023 17:38:46 +1000 [thread overview]
Message-ID: <20230120073913.1028407-11-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com>
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Some boards are duplicating the 'riscv_find_and_load_firmware' call
because the 32 and 64 bits images have different names. Create
a function to handle this detail instead of hardcoding it in the boards.
Ideally we would bake this logic inside riscv_find_and_load_firmware(),
or even create a riscv_load_default_firmware(), but at this moment we
cannot infer whether the machine is running 32 or 64 bits without
accessing RISCVHartArrayState, which in turn can't be accessed via the
common code from boot.c. In the end we would exchange 'firmware_name'
for a flag with riscv_is_32bit(), which isn't much better than what we
already have today.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 1 +
hw/riscv/boot.c | 9 +++++++++
hw/riscv/sifive_u.c | 11 ++++-------
hw/riscv/spike.c | 14 +++++---------
hw/riscv/virt.c | 10 +++-------
5 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index c03e4e74c5..60cf320c88 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -37,6 +37,7 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 7361d5c0d8..e1a544b1d9 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -75,6 +75,15 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
}
}
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
+{
+ if (riscv_is_32bit(harts)) {
+ return RISCV32_BIOS_BIN;
+ }
+
+ return RISCV64_BIOS_BIN;
+}
+
static char *riscv_find_firmware(const char *firmware_filename)
{
char *filename;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b40a4767e2..a58ddb36ac 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -533,6 +533,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
+ const char *firmware_name;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@@ -595,13 +596,9 @@ static void sifive_u_machine_init(MachineState *machine)
break;
}
- if (riscv_is_32bit(&s->soc.u_cpus)) {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV32_BIOS_BIN, start_addr, NULL);
- } else {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV64_BIOS_BIN, start_addr, NULL);
- }
+ firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ start_addr, NULL);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index df9f070707..3c8a8de673 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -190,6 +190,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
target_ulong firmware_end_addr, kernel_start_addr;
+ const char *firmware_name;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
char *soc_name;
@@ -255,15 +256,10 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
mask_rom);
- if (riscv_is_32bit(&s->soc[0])) {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
- htif_symbol_callback);
- } else {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
- htif_symbol_callback);
- }
+ firmware_name = riscv_default_firmware_name(&s->soc[0]);
+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ memmap[SPIKE_DRAM].base,
+ htif_symbol_callback);
/* Load kernel */
if (machine->kernel_filename) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 94ff2a1584..408f7a2256 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1237,6 +1237,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
MachineState *machine = MACHINE(s);
target_ulong start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
+ const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
uint32_t fdt_load_addr;
uint64_t kernel_entry;
@@ -1256,13 +1257,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
}
}
- if (riscv_is_32bit(&s->soc[0])) {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV32_BIOS_BIN, start_addr, NULL);
- } else {
- firmware_end_addr = riscv_find_and_load_firmware(machine,
- RISCV64_BIOS_BIN, start_addr, NULL);
- }
+ firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ start_addr, NULL);
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
--
2.39.0
next prev parent reply other threads:[~2023-01-20 7:41 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 7:38 [PULL 00/37] riscv-to-apply queue Alistair Francis
2023-01-20 7:38 ` [PULL 01/37] hw/char: riscv_htif: Avoid using magic numbers Alistair Francis
2023-01-20 7:38 ` [PULL 02/37] hw/char: riscv_htif: Drop {to, from}host_size in HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 03/37] hw/char: riscv_htif: Drop useless assignment of memory region Alistair Francis
2023-01-20 7:38 ` [PULL 04/37] hw/char: riscv_htif: Use conventional 's' for HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 05/37] hw/char: riscv_htif: Move registers from CPUArchState to HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables Alistair Francis
2023-01-20 7:38 ` [PULL 07/37] hw/char: riscv_htif: Support console output via proxy syscall Alistair Francis
2023-01-20 7:38 ` [PULL 08/37] hw/riscv: spike: Remove the out-of-date comments Alistair Francis
2023-01-20 7:38 ` [PULL 09/37] hw/riscv/boot.c: make riscv_find_firmware() static Alistair Francis
2023-01-20 7:38 ` Alistair Francis [this message]
2023-01-20 7:38 ` [PULL 11/37] hw/riscv/boot.c: Introduce riscv_find_firmware() Alistair Francis
2023-01-20 7:38 ` [PULL 12/37] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading Alistair Francis
2023-01-20 7:38 ` [PULL 13/37] target/riscv/cpu.c: Fix elen check Alistair Francis
2023-01-20 7:38 ` [PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test Alistair Francis
2023-01-20 7:38 ` [PULL 15/37] hw/riscv/spike: use 'fdt' from MachineState Alistair Francis
2023-01-20 7:38 ` [PULL 16/37] hw/riscv/sifive_u: " Alistair Francis
2023-01-20 7:38 ` [PULL 17/37] hw/riscv/boot.c: exit early if filename is NULL in load functions Alistair Francis
2023-01-20 7:38 ` [PULL 18/37] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 19/37] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Alistair Francis
2023-01-20 7:38 ` [PULL 20/37] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 21/37] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Alistair Francis
2023-01-20 7:38 ` [PULL 22/37] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props() Alistair Francis
2023-01-20 7:39 ` [PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Alistair Francis
2023-01-20 7:39 ` [PULL 25/37] target/riscv: Use TARGET_FMT_lx for env->mhartid Alistair Francis
2023-01-20 7:39 ` [PULL 26/37] hw/riscv/spike.c: simplify create_fdt() Alistair Francis
2023-01-20 7:39 ` [PULL 27/37] hw/riscv/virt.c: " Alistair Francis
2023-01-20 7:39 ` [PULL 28/37] hw/riscv/sifive_u.c: " Alistair Francis
2023-01-20 7:39 ` [PULL 29/37] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Alistair Francis
2023-01-20 7:39 ` [PULL 30/37] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Alistair Francis
2023-01-20 7:39 ` [PULL 31/37] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Alistair Francis
2023-01-20 7:39 ` [PULL 32/37] target/riscv: Fix up masking of vsip/vsie accesses Alistair Francis
2023-01-20 7:39 ` [PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 Alistair Francis
2023-01-20 7:39 ` [PULL 34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Alistair Francis
2023-01-20 7:39 ` [PULL 35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm Alistair Francis
2023-01-20 7:39 ` [PULL 36/37] target/riscv: Remove helper_set_rod_rounding_mode Alistair Francis
2023-01-20 7:39 ` [PULL 37/37] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() Alistair Francis
2023-01-21 13:01 ` [PULL 00/37] riscv-to-apply queue Peter Maydell
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