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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The riscv32 'spike' machine isn't bootable at this moment, requiring an OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that or add a 'skip' test to remind us about it. To work as a reminder that we have a riscv32 'spike' test that should be enabled as soon as OpenSBI QEMU rom receives the fix, we're adding a 'skip' test: (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: SKIP: requires OpenSBI fix to work [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.186= 0569-1-bmeng@tinylab.org/ [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D334159 Cc: Cleber Rosa Cc: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi= .py new file mode 100644 index 0000000000..e02f0d404a --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado import skip +from avocado_qemu import wait_for_console_pattern + +class RiscvOpenSBI(QemuSystemTest): + """ + :avocado: tags=3Daccel:tcg + """ + timeout =3D 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + @skip("requires OpenSBI fix to work") + def test_riscv32_spike(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() + + def test_riscv64_spike(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:spike + """ + self.boot_opensbi() + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:sifive_u + """ + self.boot_opensbi() + + def test_riscv32_virt(self): + """ + :avocado: tags=3Darch:riscv32 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() + + def test_riscv64_virt(self): + """ + :avocado: tags=3Darch:riscv64 + :avocado: tags=3Dmachine:virt + """ + self.boot_opensbi() --=20 2.39.0