From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Andrew Bresticker <abrestic@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 32/37] target/riscv: Fix up masking of vsip/vsie accesses
Date: Fri, 20 Jan 2023 17:39:08 +1000 [thread overview]
Message-ID: <20230120073913.1028407-33-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230120073913.1028407-1-alistair.francis@opensource.wdc.com>
From: Andrew Bresticker <abrestic@rivosinc.com>
The current logic attempts to shift the VS-level bits into their correct
position in mip while leaving the remaining bits in-tact. This is both
pointless and likely incorrect since one would expect that any new, future
VS-level interrupts will get their own position in mip rather than sharing
with their (H)S-level equivalent. Fix this, and make the logic more
readable, by just making off the VS-level bits and shifting them into
position.
This also fixes reads of vsip, which would only ever report vsip.VSSIP
since the non-writable bits got masked off as well.
Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 35 +++++++++++------------------------
1 file changed, 11 insertions(+), 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0db2c233e5..270de7b1a8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2305,22 +2305,15 @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
- uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
+ uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
- vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
- new_val &= ~(VS_MODE_INTERRUPTS >> 1);
- new_val |= vsbits << 1;
- vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
- wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
- wr_mask |= vsbits << 1;
+ new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+ wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
if (ret_val) {
- rval &= mask;
- vsbits = rval & VS_MODE_INTERRUPTS;
- rval &= ~VS_MODE_INTERRUPTS;
- *ret_val = rval | (vsbits >> 1);
+ *ret_val = (rval & mask) >> 1;
}
return ret;
@@ -2521,22 +2514,16 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
uint64_t new_val, uint64_t wr_mask)
{
RISCVException ret;
- uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
+ uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
/* Bring VS-level bits to correct position */
- vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
- new_val &= ~(VS_MODE_INTERRUPTS >> 1);
- new_val |= vsbits << 1;
- vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
- wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
- wr_mask |= vsbits << 1;
-
- ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
+ new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+ wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
+
+ ret = rmw_mip64(env, csrno, &rval, new_val,
+ wr_mask & mask & vsip_writable_mask);
if (ret_val) {
- rval &= mask;
- vsbits = rval & VS_MODE_INTERRUPTS;
- rval &= ~VS_MODE_INTERRUPTS;
- *ret_val = rval | (vsbits >> 1);
+ *ret_val = (rval & mask) >> 1;
}
return ret;
--
2.39.0
next prev parent reply other threads:[~2023-01-20 7:46 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 7:38 [PULL 00/37] riscv-to-apply queue Alistair Francis
2023-01-20 7:38 ` [PULL 01/37] hw/char: riscv_htif: Avoid using magic numbers Alistair Francis
2023-01-20 7:38 ` [PULL 02/37] hw/char: riscv_htif: Drop {to, from}host_size in HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 03/37] hw/char: riscv_htif: Drop useless assignment of memory region Alistair Francis
2023-01-20 7:38 ` [PULL 04/37] hw/char: riscv_htif: Use conventional 's' for HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 05/37] hw/char: riscv_htif: Move registers from CPUArchState to HTIFState Alistair Francis
2023-01-20 7:38 ` [PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables Alistair Francis
2023-01-20 7:38 ` [PULL 07/37] hw/char: riscv_htif: Support console output via proxy syscall Alistair Francis
2023-01-20 7:38 ` [PULL 08/37] hw/riscv: spike: Remove the out-of-date comments Alistair Francis
2023-01-20 7:38 ` [PULL 09/37] hw/riscv/boot.c: make riscv_find_firmware() static Alistair Francis
2023-01-20 7:38 ` [PULL 10/37] hw/riscv/boot.c: introduce riscv_default_firmware_name() Alistair Francis
2023-01-20 7:38 ` [PULL 11/37] hw/riscv/boot.c: Introduce riscv_find_firmware() Alistair Francis
2023-01-20 7:38 ` [PULL 12/37] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading Alistair Francis
2023-01-20 7:38 ` [PULL 13/37] target/riscv/cpu.c: Fix elen check Alistair Francis
2023-01-20 7:38 ` [PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test Alistair Francis
2023-01-20 7:38 ` [PULL 15/37] hw/riscv/spike: use 'fdt' from MachineState Alistair Francis
2023-01-20 7:38 ` [PULL 16/37] hw/riscv/sifive_u: " Alistair Francis
2023-01-20 7:38 ` [PULL 17/37] hw/riscv/boot.c: exit early if filename is NULL in load functions Alistair Francis
2023-01-20 7:38 ` [PULL 18/37] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 19/37] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Alistair Francis
2023-01-20 7:38 ` [PULL 20/37] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 21/37] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Alistair Francis
2023-01-20 7:38 ` [PULL 22/37] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Alistair Francis
2023-01-20 7:38 ` [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props() Alistair Francis
2023-01-20 7:39 ` [PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Alistair Francis
2023-01-20 7:39 ` [PULL 25/37] target/riscv: Use TARGET_FMT_lx for env->mhartid Alistair Francis
2023-01-20 7:39 ` [PULL 26/37] hw/riscv/spike.c: simplify create_fdt() Alistair Francis
2023-01-20 7:39 ` [PULL 27/37] hw/riscv/virt.c: " Alistair Francis
2023-01-20 7:39 ` [PULL 28/37] hw/riscv/sifive_u.c: " Alistair Francis
2023-01-20 7:39 ` [PULL 29/37] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Alistair Francis
2023-01-20 7:39 ` [PULL 30/37] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Alistair Francis
2023-01-20 7:39 ` [PULL 31/37] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Alistair Francis
2023-01-20 7:39 ` Alistair Francis [this message]
2023-01-20 7:39 ` [PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 Alistair Francis
2023-01-20 7:39 ` [PULL 34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Alistair Francis
2023-01-20 7:39 ` [PULL 35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm Alistair Francis
2023-01-20 7:39 ` [PULL 36/37] target/riscv: Remove helper_set_rod_rounding_mode Alistair Francis
2023-01-20 7:39 ` [PULL 37/37] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() Alistair Francis
2023-01-21 13:01 ` [PULL 00/37] riscv-to-apply queue Peter Maydell
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