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envelope-from=prvs=37747d9ec=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bin Meng At present for some unknown reason the HTIF registers (fromhost & tohost) are defined in the RISC-V CPUArchState. It should really be put in the HTIFState struct as it is only meaningful to HTIF. Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 8 ++++---- target/riscv/cpu.h | 4 ---- hw/char/riscv_htif.c | 35 +++++++++++++++++------------------ hw/riscv/spike.c | 3 +-- target/riscv/machine.c | 6 ++---- 5 files changed, 24 insertions(+), 32 deletions(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 6d172ebd6d..55cc352331 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -23,7 +23,6 @@ #include "chardev/char.h" #include "chardev/char-fe.h" #include "exec/memory.h" -#include "target/riscv/cpu.h" =20 #define TYPE_HTIF_UART "riscv.htif.uart" =20 @@ -31,11 +30,12 @@ typedef struct HTIFState { int allow_tohost; int fromhost_inprogress; =20 + uint64_t tohost; + uint64_t fromhost; hwaddr tohost_offset; hwaddr fromhost_offset; MemoryRegion mmio; =20 - CPURISCVState *env; CharBackend chr; uint64_t pending_read; } HTIFState; @@ -51,7 +51,7 @@ void htif_symbol_callback(const char *st_name, int st_i= nfo, uint64_t st_value, bool htif_uses_elf_symbols(void); =20 /* legacy pre qom */ -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, - Chardev *chr, uint64_t nonelf_base); +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, + uint64_t nonelf_base); =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..61a9a40958 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,10 +309,6 @@ struct CPUArchState { target_ulong sscratch; target_ulong mscratch; =20 - /* temporary htif regs */ - uint64_t mfromhost; - uint64_t mtohost; - /* Sstc CSRs */ uint64_t stimecmp; =20 diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index f28976b110..3bb0a37a3e 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -100,7 +100,7 @@ static void htif_recv(void *opaque, const uint8_t *bu= f, int size) uint64_t val_written =3D s->pending_read; uint64_t resp =3D 0x100 | *buf; =20 - s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16)= ; + s->fromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); } =20 /* @@ -175,7 +175,7 @@ static void htif_handle_tohost_write(HTIFState *s, ui= nt64_t val_written) if (cmd =3D=3D HTIF_CONSOLE_CMD_GETC) { /* this should be a queue, but not yet implemented as such *= / s->pending_read =3D val_written; - s->env->mtohost =3D 0; /* clear to indicate we read */ + s->tohost =3D 0; /* clear to indicate we read */ return; } else if (cmd =3D=3D HTIF_CONSOLE_CMD_PUTC) { qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); @@ -195,11 +195,11 @@ static void htif_handle_tohost_write(HTIFState *s, = uint64_t val_written) * HTIF needs protocol documentation and a more complete state machi= ne. * * while (!s->fromhost_inprogress && - * s->env->mfromhost !=3D 0x0) { + * s->fromhost !=3D 0x0) { * } */ - s->env->mfromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16)= ; - s->env->mtohost =3D 0; /* clear to indicate we read */ + s->fromhost =3D (val_written >> 48 << 48) | (resp << 16 >> 16); + s->tohost =3D 0; /* clear to indicate we read */ } =20 #define TOHOST_OFFSET1 (s->tohost_offset) @@ -212,13 +212,13 @@ static uint64_t htif_mm_read(void *opaque, hwaddr a= ddr, unsigned size) { HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - return s->env->mtohost & 0xFFFFFFFF; + return s->tohost & 0xFFFFFFFF; } else if (addr =3D=3D TOHOST_OFFSET2) { - return (s->env->mtohost >> 32) & 0xFFFFFFFF; + return (s->tohost >> 32) & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET1) { - return s->env->mfromhost & 0xFFFFFFFF; + return s->fromhost & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - return (s->env->mfromhost >> 32) & 0xFFFFFFFF; + return (s->fromhost >> 32) & 0xFFFFFFFF; } else { qemu_log("Invalid htif read: address %016" PRIx64 "\n", (uint64_t)addr); @@ -232,22 +232,22 @@ static void htif_mm_write(void *opaque, hwaddr addr= , { HTIFState *s =3D opaque; if (addr =3D=3D TOHOST_OFFSET1) { - if (s->env->mtohost =3D=3D 0x0) { + if (s->tohost =3D=3D 0x0) { s->allow_tohost =3D 1; - s->env->mtohost =3D value & 0xFFFFFFFF; + s->tohost =3D value & 0xFFFFFFFF; } else { s->allow_tohost =3D 0; } } else if (addr =3D=3D TOHOST_OFFSET2) { if (s->allow_tohost) { - s->env->mtohost |=3D value << 32; - htif_handle_tohost_write(s, s->env->mtohost); + s->tohost |=3D value << 32; + htif_handle_tohost_write(s, s->tohost); } } else if (addr =3D=3D FROMHOST_OFFSET1) { s->fromhost_inprogress =3D 1; - s->env->mfromhost =3D value & 0xFFFFFFFF; + s->fromhost =3D value & 0xFFFFFFFF; } else if (addr =3D=3D FROMHOST_OFFSET2) { - s->env->mfromhost |=3D value << 32; + s->fromhost |=3D value << 32; s->fromhost_inprogress =3D 0; } else { qemu_log("Invalid htif write: address %016" PRIx64 "\n", @@ -265,8 +265,8 @@ bool htif_uses_elf_symbols(void) return (address_symbol_set =3D=3D 3) ? true : false; } =20 -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env, - Chardev *chr, uint64_t nonelf_base) +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, + uint64_t nonelf_base) { uint64_t base, size, tohost_offset, fromhost_offset; =20 @@ -281,7 +281,6 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, = CPURISCVState *env, fromhost_offset =3D fromhost_addr - base; =20 HTIFState *s =3D g_new0(HTIFState, 1); - s->env =3D env; s->tohost_offset =3D tohost_offset; s->fromhost_offset =3D fromhost_offset; s->pending_read =3D 0; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bc4953cf4a..fb4152c2a2 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,8 +316,7 @@ static void spike_board_init(MachineState *machine) fdt_load_addr); =20 /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, &s->soc[0].harts[0].env, - serial_hd(0), memmap[SPIKE_HTIF].base); + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); } =20 static void spike_machine_instance_init(Object *obj) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 65a8549ec2..c6ce318cce 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -333,8 +333,8 @@ static const VMStateDescription vmstate_pmu_ctr_state= =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 5, - .minimum_version_id =3D 5, + .version_id =3D 6, + .minimum_version_id =3D 6, .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -384,8 +384,6 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEV= ENTS), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), - VMSTATE_UINT64(env.mfromhost, RISCVCPU), - VMSTATE_UINT64(env.mtohost, RISCVCPU), VMSTATE_UINT64(env.stimecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() --=20 2.39.0