From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, yier.jin@huawei.com,
jonathan.cameron@huawei.com, leonardo.garcia@linaro.org
Subject: [PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate
Date: Mon, 23 Jan 2023 14:00:21 -1000 [thread overview]
Message-ID: <20230124000027.3565716-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org>
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 21 +++++++--------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 37f5ff220c..eaa47f6b62 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -22,6 +22,7 @@ typedef struct S1Translate {
ARMSecuritySpace in_space;
bool in_secure;
bool in_debug;
+ bool in_s1_is_el0;
bool out_secure;
bool out_rw;
bool out_be;
@@ -33,7 +34,7 @@ typedef struct S1Translate {
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
@@ -1257,17 +1258,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
* @ptw: Current and next stage parameters for the walk.
* @address: virtual address to get physical address for
* @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
- * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
- * (so this is a stage 2 page table walk),
- * must be true if this is stage 2 of a stage 1+2
- * walk for an EL0 access. If @mmu_idx is anything else,
- * @s1_is_el0 is ignored.
* @result: set on translation success,
* @fi: set to fault info if the translation fails
*/
static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
uint64_t address,
- MMUAccessType access_type, bool s1_is_el0,
+ MMUAccessType access_type,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
@@ -1596,7 +1592,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
result->f.prot = get_S2prot_noexecute(ap);
} else {
xn = extract64(attrs, 53, 2);
- result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
+ result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0);
}
} else {
int ns = extract32(attrs, 5, 1);
@@ -2819,7 +2815,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
bool ret, ipa_secure, s2walk_secure;
ARMCacheAttrs cacheattrs1;
ARMSecuritySpace ipa_space, s2walk_space;
- bool is_el0;
uint64_t hcr;
ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi);
@@ -2844,7 +2839,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
s2walk_space = ipa_space;
}
- is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
+ ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0;
ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
ptw->in_ptw_idx = arm_space_to_phys(s2walk_space);
ptw->in_secure = s2walk_secure;
@@ -2863,8 +2858,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
ret = get_phys_addr_pmsav8(env, ipa, access_type,
ptw->in_mmu_idx, s2walk_secure, result, fi);
} else {
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
- is_el0, result, fi);
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
}
fi->s2addr = ipa;
@@ -3040,8 +3034,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
}
if (regime_using_lpae_format(env, mmu_idx)) {
- return get_phys_addr_lpae(env, ptw, address, access_type, false,
- result, fi);
+ return get_phys_addr_lpae(env, ptw, address, access_type, result, fi);
} else if (arm_feature(env, ARM_FEATURE_V7) ||
regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
--
2.34.1
next prev parent reply other threads:[~2023-01-24 0:02 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 0:00 [PATCH 00/22] target/arm: Implement FEAT_RME Richard Henderson
2023-01-24 0:00 ` [PATCH 01/22] target/arm: Fix pmsav8 stage2 secure parameter Richard Henderson
2023-02-07 14:26 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 02/22] target/arm: Rewrite check_s2_mmu_setup Richard Henderson
2023-02-07 16:00 ` Peter Maydell
2023-02-07 19:31 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 03/22] target/arm: Add isar_feature_aa64_rme Richard Henderson
2023-02-07 14:31 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 04/22] target/arm: Update SCR and HCR for RME Richard Henderson
2023-02-07 14:34 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 05/22] target/arm: SCR_EL3.NS may be RES1 Richard Henderson
2023-02-07 14:39 ` Peter Maydell
2023-02-07 19:43 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 06/22] target/arm: Add RME cpregs Richard Henderson
2023-02-07 14:53 ` Peter Maydell
2023-02-08 21:51 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 07/22] target/arm: Introduce ARMSecuritySpace Richard Henderson
2023-02-07 15:00 ` Peter Maydell
2023-02-08 22:00 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 08/22] include/exec/memattrs: Add two bits of space to MemTxAttrs Richard Henderson
2023-02-07 15:05 ` Peter Maydell
2023-02-08 22:12 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 09/22] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Richard Henderson
2023-02-07 15:07 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 10/22] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Richard Henderson
2023-02-07 15:09 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 11/22] target/arm: Pipe ARMSecuritySpace through ptw.c Richard Henderson
2023-02-07 16:15 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 12/22] target/arm: NSTable is RES0 for the RME EL3 regime Richard Henderson
2023-02-10 11:36 ` Peter Maydell
2023-02-10 19:49 ` Richard Henderson
2023-01-24 0:00 ` [PATCH 13/22] target/arm: Handle Block and Page bits for security space Richard Henderson
2023-02-10 11:53 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 14/22] target/arm: Handle no-execute for Realm and Root regimes Richard Henderson
2023-02-10 11:59 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Richard Henderson
2023-02-10 13:21 ` Peter Maydell
2023-01-24 0:00 ` Richard Henderson [this message]
2023-02-10 13:23 ` [PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate Peter Maydell
2023-01-24 0:00 ` [PATCH 17/22] target/arm: Use get_phys_addr_with_struct for stage2 Richard Henderson
2023-02-10 13:28 ` Peter Maydell
2023-02-20 22:15 ` Richard Henderson
2023-02-21 11:11 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 18/22] target/arm: Add GPC syndrome Richard Henderson
2023-02-10 13:32 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 19/22] target/arm: Implement GPC exceptions Richard Henderson
2023-02-10 13:53 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 20/22] target/arm: Implement the granule protection check Richard Henderson
2023-02-10 14:18 ` Peter Maydell
2023-01-24 0:00 ` [PATCH 21/22] target/arm: Enable RME for -cpu max Richard Henderson
2023-02-10 14:20 ` Peter Maydell
2023-02-20 23:31 ` Richard Henderson
2023-01-24 0:00 ` [RFC PATCH 22/22] hw/arm/virt: Add some memory for Realm Management Monitor Richard Henderson
2023-02-10 14:24 ` Peter Maydell
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