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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "WANG Xuerui" <git@xen0n.name>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 10/15] tcg/loongarch64: Update tcg-insn-defs.c.inc
Date: Mon, 23 Jan 2023 16:05:02 -1000	[thread overview]
Message-ID: <20230124020507.3732200-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230124020507.3732200-1-richard.henderson@linaro.org>

Regenerate with ADDU16I included:

   $ cd loongarch-opcodes/scripts/go
   $ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc

Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-insn-defs.c.inc | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg-insn-defs.c.inc
index d162571856..b5bb0c5e73 100644
--- a/tcg/loongarch64/tcg-insn-defs.c.inc
+++ b/tcg/loongarch64/tcg-insn-defs.c.inc
@@ -4,7 +4,7 @@
  *
  * This file is auto-generated by genqemutcgdefs from
  * https://github.com/loongson-community/loongarch-opcodes,
- * from commit 961f0c60f5b63e574d785995600c71ad5413fdc4.
+ * from commit 25ca7effe9d88101c1cf96c4005423643386d81f.
  * DO NOT EDIT.
  */
 
@@ -74,6 +74,7 @@ typedef enum {
     OPC_ANDI = 0x03400000,
     OPC_ORI = 0x03800000,
     OPC_XORI = 0x03c00000,
+    OPC_ADDU16I_D = 0x10000000,
     OPC_LU12I_W = 0x14000000,
     OPC_CU32I_D = 0x16000000,
     OPC_PCADDU2I = 0x18000000,
@@ -710,6 +711,13 @@ tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
     tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12));
 }
 
+/* Emits the `addu16i.d d, j, sk16` instruction.  */
+static void __attribute__((unused))
+tcg_out_opc_addu16i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
+{
+    tcg_out32(s, encode_djsk16_insn(OPC_ADDU16I_D, d, j, sk16));
+}
+
 /* Emits the `lu12i.w d, sj20` instruction.  */
 static void __attribute__((unused))
 tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20)
-- 
2.34.1



  parent reply	other threads:[~2023-01-24  2:07 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-24  2:04 [PULL v2 00/15] tcg patch queue Richard Henderson
2023-01-24  2:04 ` [PULL v2 01/15] tcg: Avoid recursion in tcg_gen_mulu2_i32 Richard Henderson
2023-01-24  2:04 ` [PULL v2 02/15] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64 Richard Henderson
2023-01-24  2:04 ` [PULL v2 03/15] common-user/host/ppc: Implement safe-syscall.inc.S Richard Henderson
2023-01-24  2:04 ` [PULL v2 04/15] linux-user: Implment host/ppc/host-signal.h Richard Henderson
2023-01-24  2:04 ` [PULL v2 05/15] tcg: Mark tcg helpers noinline to avoid an issue with LTO Richard Henderson
2023-01-24  2:04 ` [PULL v2 06/15] target/loongarch: Enable the disassembler for host tcg Richard Henderson
2023-01-24  2:04 ` [PULL v2 07/15] target/loongarch: Disassemble jirl properly Richard Henderson
2023-01-24  2:05 ` [PULL v2 08/15] target/loongarch: Disassemble pcadd* addresses Richard Henderson
2023-01-24  2:05 ` [PULL v2 09/15] tcg/loongarch64: Optimize immediate loading Richard Henderson
2023-01-24  2:05 ` Richard Henderson [this message]
2023-01-24  2:05 ` [PULL v2 11/15] tcg/loongarch64: Introduce tcg_out_addi Richard Henderson
2023-01-24  2:05 ` [PULL v2 12/15] tcg/loongarch64: Improve setcond expansion Richard Henderson
2023-01-24  2:05 ` [PULL v2 13/15] tcg/loongarch64: Implement movcond Richard Henderson
2023-01-24  2:05 ` [PULL v2 14/15] tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst Richard Henderson
2023-01-24  2:05 ` [PULL v2 15/15] tcg/loongarch64: Reorg goto_tb implementation Richard Henderson
2023-02-03 12:42 ` [PULL v2 00/15] tcg patch queue Peter Maydell

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