From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL v2 02/15] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64
Date: Mon, 23 Jan 2023 16:04:54 -1000 [thread overview]
Message-ID: <20230124020507.3732200-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230124020507.3732200-1-richard.henderson@linaro.org>
Although we still can't use ldrd and strd for all operations,
increase the chances by getting the register allocation correct.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-con-set.h | 7 ++++---
tcg/arm/tcg-target-con-str.h | 2 ++
tcg/arm/tcg-target.c.inc | 28 ++++++++++++++++++----------
3 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index 3685e1786a..b8849b2478 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -15,8 +15,9 @@ C_O0_I2(r, rIN)
C_O0_I2(s, s)
C_O0_I2(w, r)
C_O0_I3(s, s, s)
+C_O0_I3(S, p, s)
C_O0_I4(r, r, rI, rI)
-C_O0_I4(s, s, s, s)
+C_O0_I4(S, p, s, s)
C_O1_I1(r, l)
C_O1_I1(r, r)
C_O1_I1(w, r)
@@ -38,8 +39,8 @@ C_O1_I2(w, w, wZ)
C_O1_I3(w, w, w, w)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
-C_O2_I1(r, r, l)
-C_O2_I2(r, r, l, l)
+C_O2_I1(e, p, l)
+C_O2_I2(e, p, l, l)
C_O2_I2(r, r, r, r)
C_O2_I4(r, r, r, r, rIN, rIK)
C_O2_I4(r, r, rI, rI, rIN, rIK)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index 8f501149e1..24b4b59feb 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -8,9 +8,11 @@
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
+REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
REGS('r', ALL_GENERAL_REGS)
REGS('l', ALL_QLOAD_REGS)
REGS('s', ALL_QSTORE_REGS)
+REGS('S', ALL_QSTORE_REGS & 0x5555) /* even qstore */
REGS('w', ALL_VECTOR_REGS)
/*
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 6abe94137e..0f5f9f4925 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1694,9 +1694,11 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
break;
case MO_UQ:
+ /* We used pair allocation for datalo, so already should be aligned. */
+ tcg_debug_assert((datalo & 1) == 0);
+ tcg_debug_assert(datahi == datalo + 1);
/* LDRD requires alignment; double-check that. */
- if (get_alignment_bits(opc) >= MO_64
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (get_alignment_bits(opc) >= MO_64) {
/*
* Rm (the second address op) must not overlap Rt or Rt + 1.
* Since datalo is aligned, we can simplify the test via alignment.
@@ -1750,9 +1752,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_UQ:
+ /* We used pair allocation for datalo, so already should be aligned. */
+ tcg_debug_assert((datalo & 1) == 0);
+ tcg_debug_assert(datahi == datalo + 1);
/* LDRD requires alignment; double-check that. */
- if (get_alignment_bits(opc) >= MO_64
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (get_alignment_bits(opc) >= MO_64) {
tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0);
} else if (datalo == addrlo) {
tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
@@ -1834,9 +1838,11 @@ static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc,
tcg_out_st32_r(s, cond, datalo, addrlo, addend);
break;
case MO_64:
+ /* We used pair allocation for datalo, so already should be aligned. */
+ tcg_debug_assert((datalo & 1) == 0);
+ tcg_debug_assert(datahi == datalo + 1);
/* STRD requires alignment; double-check that. */
- if (get_alignment_bits(opc) >= MO_64
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (get_alignment_bits(opc) >= MO_64) {
tcg_out_strd_r(s, cond, datalo, addrlo, addend);
} else if (scratch_addend) {
tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
@@ -1871,9 +1877,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_64:
+ /* We used pair allocation for datalo, so already should be aligned. */
+ tcg_debug_assert((datalo & 1) == 0);
+ tcg_debug_assert(datahi == datalo + 1);
/* STRD requires alignment; double-check that. */
- if (get_alignment_bits(opc) >= MO_64
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (get_alignment_bits(opc) >= MO_64) {
tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
} else {
tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
@@ -2372,11 +2380,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_qemu_ld_i32:
return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
case INDEX_op_qemu_ld_i64:
- return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
+ return TARGET_LONG_BITS == 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, p, l, l);
case INDEX_op_qemu_st_i32:
return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
case INDEX_op_qemu_st_i64:
- return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
+ return TARGET_LONG_BITS == 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, p, s, s);
case INDEX_op_st_vec:
return C_O0_I2(w, r);
--
2.34.1
next prev parent reply other threads:[~2023-01-24 2:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 2:04 [PULL v2 00/15] tcg patch queue Richard Henderson
2023-01-24 2:04 ` [PULL v2 01/15] tcg: Avoid recursion in tcg_gen_mulu2_i32 Richard Henderson
2023-01-24 2:04 ` Richard Henderson [this message]
2023-01-24 2:04 ` [PULL v2 03/15] common-user/host/ppc: Implement safe-syscall.inc.S Richard Henderson
2023-01-24 2:04 ` [PULL v2 04/15] linux-user: Implment host/ppc/host-signal.h Richard Henderson
2023-01-24 2:04 ` [PULL v2 05/15] tcg: Mark tcg helpers noinline to avoid an issue with LTO Richard Henderson
2023-01-24 2:04 ` [PULL v2 06/15] target/loongarch: Enable the disassembler for host tcg Richard Henderson
2023-01-24 2:04 ` [PULL v2 07/15] target/loongarch: Disassemble jirl properly Richard Henderson
2023-01-24 2:05 ` [PULL v2 08/15] target/loongarch: Disassemble pcadd* addresses Richard Henderson
2023-01-24 2:05 ` [PULL v2 09/15] tcg/loongarch64: Optimize immediate loading Richard Henderson
2023-01-24 2:05 ` [PULL v2 10/15] tcg/loongarch64: Update tcg-insn-defs.c.inc Richard Henderson
2023-01-24 2:05 ` [PULL v2 11/15] tcg/loongarch64: Introduce tcg_out_addi Richard Henderson
2023-01-24 2:05 ` [PULL v2 12/15] tcg/loongarch64: Improve setcond expansion Richard Henderson
2023-01-24 2:05 ` [PULL v2 13/15] tcg/loongarch64: Implement movcond Richard Henderson
2023-01-24 2:05 ` [PULL v2 14/15] tcg/loongarch64: Use tcg_pcrel_diff in tcg_out_ldst Richard Henderson
2023-01-24 2:05 ` [PULL v2 15/15] tcg/loongarch64: Reorg goto_tb implementation Richard Henderson
2023-02-03 12:42 ` [PULL v2 00/15] tcg patch queue Peter Maydell
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