From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Frank Chang <frank.chang@sifive.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities
Date: Tue, 24 Jan 2023 16:31:54 +0100 [thread overview]
Message-ID: <20230124153154.rtffytklzyeidd6b@orel> (raw)
In-Reply-To: <CAHVXubjvwF+VOqKSXOF8WZsjY+NzEEXVKyAxh+L02Shu0TKASA@mail.gmail.com>
On Tue, Jan 24, 2023 at 11:07:53AM +0100, Alexandre Ghiti wrote:
> On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > > Currently, the max satp mode is set with the only constraint that it must be
> > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> > >
> > > But we actually need to add another level of constraint: what the hw is
> > > actually capable of, because currently, a linux booting on a sifive-u54
> > > boots in sv57 mode which is incompatible with the cpu's sv39 max
> > > capability.
> > >
> > > So add a new bitmap to RISCVSATPMap which contains this capability and
> > > initialize it in every XXX_cpu_init.
> > >
> > > Finally, we have the following chain of constraints:
> > >
> > > Qemu capability > HW capability > User choice > Software capability
> >
> > ^ What software is this?
> > I'd think the user's choice would always be last.
>
> Hmm maybe that's not clear, but I meant that the last constraint was
> what the emulated software is capable of handling.
Assuming "emulated software" is the guest OS, then OK. How about rewording
as
target/riscv's general satp mode support constrains what the boards
support and the boards constrain what the user may select. The user's
selection will then constrain what's available to the guest OS.
Thanks,
drew
next prev parent reply other threads:[~2023-01-24 15:32 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-23 9:03 [PATCH v6 0/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-23 9:03 ` [PATCH v6 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Alexandre Ghiti
2023-01-23 9:03 ` [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Alexandre Ghiti
2023-01-23 9:48 ` Andrew Jones
2023-01-24 0:02 ` Alistair Francis
2023-01-23 9:03 ` [PATCH v6 3/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-23 10:11 ` Andrew Jones
2023-01-24 9:56 ` Alexandre Ghiti
2023-01-23 10:14 ` Andrew Jones
2023-01-24 9:56 ` Alexandre Ghiti
2023-01-23 10:29 ` Andrew Jones
2023-01-24 10:00 ` Alexandre Ghiti
2023-01-23 9:03 ` [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' Alexandre Ghiti
2023-01-23 10:12 ` Andrew Jones
2023-01-24 0:35 ` Alistair Francis
2023-01-23 9:03 ` [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Alexandre Ghiti
2023-01-23 10:51 ` Andrew Jones
2023-01-23 11:15 ` Alexandre Ghiti
2023-01-23 13:31 ` Andrew Jones
2023-01-24 13:13 ` Alexandre Ghiti
2023-01-24 10:07 ` Alexandre Ghiti
2023-01-24 15:31 ` Andrew Jones [this message]
2023-01-23 13:51 ` Andrew Jones
2023-01-24 13:24 ` Alexandre Ghiti
2023-01-24 0:41 ` Alistair Francis
2023-01-24 9:13 ` Alexandre Ghiti
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