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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id u4-20020a17090617c400b0081bfc79beaesm1026873eje.75.2023.01.24.07.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 07:31:55 -0800 (PST) Date: Tue, 24 Jan 2023 16:31:54 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230124153154.rtffytklzyeidd6b@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jan 24, 2023 at 11:07:53AM +0100, Alexandre Ghiti wrote: > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > > Currently, the max satp mode is set with the only constraint that it must be > > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > > > But we actually need to add another level of constraint: what the hw is > > > actually capable of, because currently, a linux booting on a sifive-u54 > > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > > capability. > > > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > > initialize it in every XXX_cpu_init. > > > > > > Finally, we have the following chain of constraints: > > > > > > Qemu capability > HW capability > User choice > Software capability > > > > ^ What software is this? > > I'd think the user's choice would always be last. > > Hmm maybe that's not clear, but I meant that the last constraint was > what the emulated software is capable of handling. Assuming "emulated software" is the guest OS, then OK. How about rewording as target/riscv's general satp mode support constrains what the boards support and the boards constrain what the user may select. The user's selection will then constrain what's available to the guest OS. Thanks, drew