From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: Eduardo Habkost <eduardo@habkost.net>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
qemu-trivial@nongnu.org, Bernhard Beschow <shentey@gmail.com>
Subject: [PATCH 3/7] hw/i386/ich9: Rename Q35_MASK to ICH9_MASK
Date: Fri, 27 Jan 2023 17:47:14 +0100 [thread overview]
Message-ID: <20230127164718.98156-4-shentey@gmail.com> (raw)
In-Reply-To: <20230127164718.98156-1-shentey@gmail.com>
The Q35_MASK macro is already defined by TYPE_Q35_HOST_DEVICE, so let
TYPE_ICH9_LPC_DEVICE have its own one to prevent potential name
collisions.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
include/hw/i386/ich9.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 222781e8b9..36e0ccd16a 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -75,7 +75,7 @@ struct ICH9LPCState {
qemu_irq gsi[GSI_NUM_PINS];
};
-#define Q35_MASK(bit, ms_bit, ls_bit) \
+#define ICH9_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
/* ICH9: Chipset Configuration Registers */
@@ -137,13 +137,13 @@ struct ICH9LPCState {
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
#define ICH9_LPC_PMBASE 0x40
-#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
+#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE 0x1
#define ICH9_LPC_PMBASE_DEFAULT 0x1
#define ICH9_LPC_ACPI_CTRL 0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
-#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
+#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9 0x0
#define ICH9_LPC_ACPI_CTRL_10 0x1
#define ICH9_LPC_ACPI_CTRL_11 0x2
@@ -162,7 +162,7 @@ struct ICH9LPCState {
#define ICH9_LPC_PIRQH_ROUT 0x6b
#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
-#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
+#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
#define ICH9_LPC_GEN_PMCON_1 0xa0
@@ -172,7 +172,7 @@ struct ICH9LPCState {
#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
#define ICH9_LPC_RCBA 0xf0
-#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
+#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN 0x1
#define ICH9_LPC_RCBA_DEFAULT 0x0
--
2.39.1
next prev parent reply other threads:[~2023-01-27 16:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-27 16:47 [PATCH 0/7] PC cleanups Bernhard Beschow
2023-01-27 16:47 ` [PATCH 1/7] hw/pci-host/i440fx: Inline sysbus_add_io() Bernhard Beschow
2023-01-27 16:47 ` [PATCH 2/7] hw/pci-host/q35: " Bernhard Beschow
2023-01-27 16:47 ` Bernhard Beschow [this message]
2023-01-27 16:47 ` [PATCH 4/7] hw/i386/pc_q35: Resolve redundant q35_host variable Bernhard Beschow
2023-01-27 19:22 ` BALATON Zoltan
2023-01-29 13:14 ` Bernhard Beschow
2023-01-29 14:37 ` BALATON Zoltan
2023-01-27 16:47 ` [PATCH 5/7] hw/i386/pc_{q35, piix}: Reuse MachineClass::desc as SMB product name Bernhard Beschow
2023-01-27 23:53 ` Philippe Mathieu-Daudé
2023-01-27 16:47 ` [PATCH 6/7] hw/i386/pc_{q35, piix}: Minimize usage of get_system_memory() Bernhard Beschow
2023-01-27 19:30 ` BALATON Zoltan
2023-01-29 11:28 ` Bernhard Beschow
2023-01-27 16:47 ` [PATCH 7/7] hw/i386/pc: Initialize ram_memory variable directly Bernhard Beschow
2023-01-27 23:57 ` Philippe Mathieu-Daudé
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