From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>
Cc: "Ben Widawsky" <bwidawsk@kernel.org>,
linux-cxl@vger.kernel.org, linuxarm@huawei.com,
"Ira Weiny" <ira.weiny@intel.com>,
"Gregory Price" <gourry.memverge@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v3 03/10] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
Date: Mon, 30 Jan 2023 14:36:58 +0000 [thread overview]
Message-ID: <20230130143705.11758-4-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20230130143705.11758-1-Jonathan.Cameron@huawei.com>
From: Gregory Price <gourry.memverge@gmail.com>
Current code sets to STORAGE_EXPRESS and then overrides it.
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 252822bd82..217a5e639b 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -408,7 +408,6 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
}
pci_config_set_prog_interface(pci_conf, 0x10);
- pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL);
pcie_endpoint_cap_init(pci_dev, 0x80);
if (ct3d->sn != UI64_NULL) {
@@ -627,7 +626,7 @@ static void ct3_class_init(ObjectClass *oc, void *data)
pc->realize = ct3_realize;
pc->exit = ct3_exit;
- pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
+ pc->class_id = PCI_CLASS_MEMORY_CXL;
pc->vendor_id = PCI_VENDOR_ID_INTEL;
pc->device_id = 0xd93; /* LVF for now */
pc->revision = 1;
--
2.37.2
next prev parent reply other threads:[~2023-01-30 14:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 14:36 [PATCH v3 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream Jonathan Cameron via
2023-01-30 14:36 ` [PATCH v3 01/10] hw/mem/cxl_type3: Improve error handling in realize() Jonathan Cameron via
2023-01-30 14:36 ` [PATCH v3 02/10] hw/pci-bridge/cxl_downstream: Fix type naming mismatch Jonathan Cameron via
2023-01-30 14:36 ` Jonathan Cameron via [this message]
2023-01-30 14:36 ` [PATCH v3 04/10] hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 05/10] tests/acpi: Allow update of q35/DSDT.cxl Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 06/10] hw/i386/acpi: Drop duplicate _UID entry for CXL root bridge Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 07/10] tests/acpi: Update q35/DSDT.cxl for removed duplicate _UID Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 08/10] qemu/bswap: Add const_le64() Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 09/10] qemu/uuid: Add UUID static initializer Jonathan Cameron via
2023-01-30 14:37 ` [PATCH v3 10/10] hw/cxl/mailbox: Use new UUID network order define for cel_uuid Jonathan Cameron via
2023-01-30 15:07 ` [PATCH v3 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream Gregory Price
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