From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de, anton.kochkov@proton.me,
richard.henderson@linaro.org
Subject: [PATCH v2 04/10] tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
Date: Thu, 2 Feb 2023 13:04:26 +0100 [thread overview]
Message-ID: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230202120432.1268-1-kbastian@mail.uni-paderborn.de>
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 16 ++++++++++++----
tests/tcg/tricore/test_insert.S | 9 +++++++++
3 files changed, 22 insertions(+), 4 deletions(-)
create mode 100644 tests/tcg/tricore/test_insert.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index bc0cfae8d0..afabba8631 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -11,6 +11,7 @@ TESTS += test_fadd.tst
TESTS += test_fmul.tst
TESTS += test_ftoi.tst
TESTS += test_imask.tst
+TESTS += test_insert.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index ceb7e9c0b7..4f2bc3cb0f 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -9,10 +9,10 @@
/* Register definitions */
#define DREG_RS1 %d0
#define DREG_RS2 %d1
-#define DREG_RS3 %d4
-#define DREG_CALC_RESULT %d1
-#define DREG_CALC_PSW %d2
-#define DREG_CORRECT_PSW %d3
+#define DREG_RS3 %d2
+#define DREG_CALC_RESULT %d3
+#define DREG_CALC_PSW %d4
+#define DREG_CORRECT_PSW %d5
#define DREG_TEMP_LI %d10
#define DREG_TEMP %d11
#define DREG_TEST_NUM %d14
@@ -103,6 +103,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
+#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/test_insert.S b/tests/tcg/tricore/test_insert.S
new file mode 100644
index 0000000000..d5fd2237e1
--- /dev/null
+++ b/tests/tcg/tricore/test_insert.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 imm1 rs2 imm2
+# | | | | | | |
+ TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
+
+ TEST_PASSFAIL
--
2.39.1
next prev parent reply other threads:[~2023-02-02 12:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-02 12:04 [PATCH v2 00/10] TriCore instruction bugfixes Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 01/10] target/tricore: Fix OPC2_32_RCRW_IMASK translation Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 02/10] tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 03/10] target/tricore: Fix OPC2_32_RCRW_INSERT translation Bastian Koppelmann
2023-02-02 12:04 ` Bastian Koppelmann [this message]
2023-02-02 12:04 ` [PATCH v2 05/10] target/tricore: Fix RRPW_DEXTR Bastian Koppelmann
2023-02-02 15:52 ` Richard Henderson
2023-02-02 12:04 ` [PATCH v2 06/10] tests/tcg/tricore: Add tests for RRPW_DEXTR Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 07/10] target/tricore: Fix OPC2_32_RRRR_DEXTR Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 08/10] tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 09/10] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC Bastian Koppelmann
2023-02-02 12:04 ` [PATCH v2 10/10] tests/tcg/tricore: Add LD.BU tests Bastian Koppelmann
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