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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id l3-20020aa7c3c3000000b004a22ed9030csm7562513edr.56.2023.02.02.03.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 03:05:33 -0800 (PST) Date: Thu, 2 Feb 2023 12:05:33 +0100 From: Igor Mammedov To: Lei Wang Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com Subject: Re: [PATCH v3 0/6] Support for new CPU model SapphireRapids Message-ID: <20230202120533.37972585@imammedo.users.ipa.redhat.com> In-Reply-To: <20230106083826.5384-1-lei4.wang@intel.com> References: <20230106083826.5384-1-lei4.wang@intel.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.36; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, 6 Jan 2023 00:38:20 -0800 Lei Wang wrote: > This series aims to add a new CPU model SapphireRapids, and tries to > address the problem stated in > https://lore.kernel.org/all/20220812055751.14553-1-lei4.wang@intel.com/T/#mcf67dbd1ad37c65d7988c36a2b267be9afd2fb30, > so that named CPU model can define its own AMX values, and QEMU won't > pass the wrong AMX values to KVM in future platforms if they have > different values supported. > > The original patch is > https://lore.kernel.org/all/20220812055751.14553-1-lei4.wang@intel.com/T/#u. MultiBitFeatureInfo looks like an interesting idea but among fixing whatever issues this has atm, you'd probably need to introduce a new qdev_bitfield property infrastructure so that such features could be treated like any other qdev properties. Also when MultiBitFeatureInfo is added, one should convert all other usecases where it's applicable (not only for new code) so that we would end up with consolidated approach instead of zoo mess. I'm not sure all MultiBitFeatureInfo complexity is necessary just for adding a new CPU model, I'd rather use ad hoc approach that we were using before for non boolean features. And then try to develop MultiBitFeatureInfo & co as a separate series to demonstrate how much it will improve current cpu models definitions. PS: 'make check-acceptance' are broken with this > --- > > Changelog: > > v3: > - Rebase on the latest QEMU (d1852caab131ea898134fdcea8c14bc2ee75fbe9). > - v2: https://lore.kernel.org/qemu-devel/20221102085256.81139-1-lei4.wang@intel.com/ > > v2: > - Fix when passing all zeros of AMX-related CPUID, QEMU will warn > unsupported. > - Remove unnecessary function definition and make code cleaner. > - Fix some typos. > - v1: https://lore.kernel.org/qemu-devel/20221027020036.373140-1-lei4.wang@intel.com/T/#t > > > Lei Wang (6): > i386: Introduce FeatureWordInfo for AMX CPUID leaf 0x1D and 0x1E > i386: Remove unused parameter "uint32_t bit" in > feature_word_description() > i386: Introduce new struct "MultiBitFeatureInfo" for multi-bit > features > i386: Mask and report unavailable multi-bit feature values > i386: Initialize AMX CPUID leaves with corresponding env->features[] > leaves > i386: Add new CPU model SapphireRapids > > target/i386/cpu-internal.h | 11 ++ > target/i386/cpu.c | 311 +++++++++++++++++++++++++++++++++++-- > target/i386/cpu.h | 16 ++ > 3 files changed, 322 insertions(+), 16 deletions(-) > > > base-commit: d1852caab131ea898134fdcea8c14bc2ee75fbe9