[PULL 00/33] target-arm queue

[Peter Maydell <peter.maydell@linaro.org>]

The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:

  Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203

for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:

  target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix physical address resolution for Stage2
 * pl011: refactoring, implement reset method
 * Support GICv3 with hvf acceleration
 * sbsa-ref: remove cortex-a76 from list of supported cpus
 * Correct syndrome for ATS12NSO* traps at Secure EL1
 * Fix priority of HSTR_EL2 traps vs UNDEFs
 * Implement FEAT_FGT for '-cpu max'

----------------------------------------------------------------
Alexander Graf (3):
      hvf: arm: Add support for GICv3
      hw/arm/virt: Consolidate GIC finalize logic
      hw/arm/virt: Make accels in GIC finalize logic explicit

Evgeny Iakovlev (4):
      hw/char/pl011: refactor FIFO depth handling code
      hw/char/pl011: add post_load hook for backwards-compatibility
      hw/char/pl011: implement a reset method
      hw/char/pl011: better handling of FIFO flags on LCR reset

Marcin Juszkiewicz (1):
      sbsa-ref: remove cortex-a76 from list of supported cpus

Peter Maydell (23):
      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
      target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
      target/arm: Move do_coproc_insn() syndrome calculation earlier
      target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
      target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
      target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
      target/arm: Define the FEAT_FGT registers
      target/arm: Implement FGT trapping infrastructure
      target/arm: Mark up sysregs for HFGRTR bits 0..11
      target/arm: Mark up sysregs for HFGRTR bits 12..23
      target/arm: Mark up sysregs for HFGRTR bits 24..35
      target/arm: Mark up sysregs for HFGRTR bits 36..63
      target/arm: Mark up sysregs for HDFGRTR bits 0..11
      target/arm: Mark up sysregs for HDFGRTR bits 12..63
      target/arm: Mark up sysregs for HFGITR bits 0..11
      target/arm: Mark up sysregs for HFGITR bits 12..17
      target/arm: Mark up sysregs for HFGITR bits 18..47
      target/arm: Mark up sysregs for HFGITR bits 48..63
      target/arm: Implement the HFGITR_EL2.ERET trap
      target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
      target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
      target/arm: Enable FEAT_FGT on '-cpu max'

Richard Henderson (2):
      hw/arm: Use TYPE_ARM_SMMUV3
      target/arm: Fix physical address resolution for Stage2

 docs/system/arm/emulation.rst |   1 +
 include/hw/arm/virt.h         |  15 +-
 include/hw/char/pl011.h       |   5 +-
 target/arm/cpregs.h           | 484 +++++++++++++++++++++++++++++++++++++++++-
 target/arm/cpu.h              |  18 ++
 target/arm/internals.h        |  20 ++
 target/arm/syndrome.h         |  10 +
 target/arm/translate.h        |   6 +
 hw/arm/sbsa-ref.c             |   4 +-
 hw/arm/virt.c                 | 203 +++++++++---------
 hw/char/pl011.c               |  93 ++++++--
 hw/intc/arm_gicv3_cpuif.c     |  18 +-
 target/arm/cpu64.c            |   1 +
 target/arm/debug_helper.c     |  46 +++-
 target/arm/helper.c           | 245 ++++++++++++++++++++-
 target/arm/hvf/hvf.c          | 151 +++++++++++++
 target/arm/op_helper.c        |  58 ++++-
 target/arm/ptw.c              |   2 +-
 target/arm/translate-a64.c    |  22 +-
 target/arm/translate.c        | 125 +++++++----
 target/arm/hvf/trace-events   |   2 +
 21 files changed, 1340 insertions(+), 189 deletions(-)