From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11
Date: Fri, 3 Feb 2023 14:29:20 +0000 [thread overview]
Message-ID: <20230203142927.834793-27-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org>
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
---
target/arm/cpregs.h | 14 ++++++++++++++
target/arm/helper.c | 28 ++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index c37e013b8f3..6596c2a1233 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -646,6 +646,20 @@ typedef enum FGTBit {
DO_BIT(HDFGWTR, PMCR_EL0),
DO_BIT(HDFGRTR, PMMIR_EL1),
DO_BIT(HDFGRTR, PMCEIDN_EL0),
+
+ /* Trap bits in HFGITR_EL2, starting from bit 0 */
+ DO_BIT(HFGITR, ICIALLUIS),
+ DO_BIT(HFGITR, ICIALLU),
+ DO_BIT(HFGITR, ICIVAU),
+ DO_BIT(HFGITR, DCIVAC),
+ DO_BIT(HFGITR, DCISW),
+ DO_BIT(HFGITR, DCCSW),
+ DO_BIT(HFGITR, DCCISW),
+ DO_BIT(HFGITR, DCCVAU),
+ DO_BIT(HFGITR, DCCVAP),
+ DO_BIT(HFGITR, DCCVADP),
+ DO_BIT(HFGITR, DCCIVAC),
+ DO_BIT(HFGITR, DCZVA),
} FGTBit;
#undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2e494b8f924..51866ba70e9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5261,6 +5261,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
.accessfn = aa64_zva_access,
+ .fgt = FGT_DCZVA,
#endif
},
{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
@@ -5270,21 +5271,26 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
+ .fgt = FGT_ICIALLUIS,
.accessfn = access_ticab },
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
+ .fgt = FGT_ICIALLU,
.accessfn = access_tocu },
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
+ .fgt = FGT_ICIVAU,
.accessfn = access_tocu },
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
+ .fgt = FGT_DCIVAC,
.type = ARM_CP_NOP },
{ .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
+ .fgt = FGT_DCISW,
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
@@ -5292,17 +5298,21 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
+ .fgt = FGT_DCCSW,
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
+ .fgt = FGT_DCCVAU,
.accessfn = access_tocu },
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
+ .fgt = FGT_DCCIVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
+ .fgt = FGT_DCCISW,
.access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
/* TLBI operations */
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
@@ -7413,6 +7423,7 @@ static const ARMCPRegInfo dcpop_reg[] = {
{ .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .fgt = FGT_DCCVAP,
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
};
@@ -7420,6 +7431,7 @@ static const ARMCPRegInfo dcpodp_reg[] = {
{ .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .fgt = FGT_DCCVADP,
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
};
#endif /*CONFIG_USER_ONLY*/
@@ -7499,28 +7511,36 @@ static const ARMCPRegInfo mte_reginfo[] = {
{ .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
.type = ARM_CP_NOP, .access = PL1_W,
+ .fgt = FGT_DCIVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+ .fgt = FGT_DCISW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL1_W,
+ .fgt = FGT_DCIVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+ .fgt = FGT_DCISW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+ .fgt = FGT_DCCSW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+ .fgt = FGT_DCCSW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+ .fgt = FGT_DCCISW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+ .fgt = FGT_DCCISW,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
};
@@ -7542,26 +7562,32 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVAP,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVAP,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVADP,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVADP,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCIVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCIVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
@@ -7569,6 +7595,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
.accessfn = aa64_zva_access,
+ .fgt = FGT_DCZVA,
#endif
},
{ .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
@@ -7577,6 +7604,7 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
.accessfn = aa64_zva_access,
+ .fgt = FGT_DCZVA,
#endif
},
};
--
2.34.1
next prev parent reply other threads:[~2023-02-03 14:32 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 14:28 [PULL 00/33] target-arm queue Peter Maydell
2023-02-03 14:28 ` [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3 Peter Maydell
2023-02-03 14:28 ` [PULL 02/33] target/arm: Fix physical address resolution for Stage2 Peter Maydell
2023-02-03 14:28 ` [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code Peter Maydell
2023-02-03 14:28 ` [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility Peter Maydell
2023-02-03 14:28 ` [PULL 05/33] hw/char/pl011: implement a reset method Peter Maydell
2023-02-03 14:29 ` [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset Peter Maydell
2023-02-03 14:29 ` [PULL 07/33] hvf: arm: Add support for GICv3 Peter Maydell
2023-02-03 14:29 ` [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic Peter Maydell
2023-02-03 14:29 ` [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit Peter Maydell
2023-02-03 14:29 ` [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus Peter Maydell
2023-02-03 14:29 ` [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Peter Maydell
2023-02-03 14:29 ` [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Peter Maydell
2023-02-03 14:29 ` [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier Peter Maydell
2023-02-03 14:29 ` [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Peter Maydell
2023-02-03 14:29 ` [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Peter Maydell
2023-02-03 14:29 ` [PULL 18/33] target/arm: Define the FEAT_FGT registers Peter Maydell
2023-02-03 14:29 ` [PULL 19/33] target/arm: Implement FGT trapping infrastructure Peter Maydell
2023-02-03 14:29 ` [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Peter Maydell
2023-02-03 14:29 ` [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35 Peter Maydell
2023-02-03 14:29 ` [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 Peter Maydell
2023-02-03 14:29 ` [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Peter Maydell
2023-02-03 14:29 ` Peter Maydell [this message]
2023-02-03 14:29 ` [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17 Peter Maydell
2023-02-03 14:29 ` [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47 Peter Maydell
2023-02-03 14:29 ` [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Peter Maydell
2023-02-03 14:29 ` [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap Peter Maydell
2023-02-03 14:29 ` [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Peter Maydell
2023-02-03 14:29 ` [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Peter Maydell
2023-02-03 14:29 ` [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' Peter Maydell
2023-02-03 18:54 ` [PULL 00/33] target-arm queue Peter Maydell
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