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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility
Date: Fri,  3 Feb 2023 14:28:58 +0000	[thread overview]
Message-ID: <20230203142927.834793-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org>

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single-register-deep FIFO now. Then we changed it to always store data
at pos 0.

If guest disables FIFO and the proceeds to read data, it will work out
fine, because we still read from current read_pos before setting it to
0.

However, to make code less fragile, introduce a post_load hook for
PL011State and move fixup read FIFO state when FIFO is disabled. Since
we are introducing a post_load hook, also do some sanity checking on
untrusted incoming input state.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 3fa3b75d042..05e8bdc050e 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -352,10 +352,35 @@ static const VMStateDescription vmstate_pl011_clock = {
     }
 };
 
+static int pl011_post_load(void *opaque, int version_id)
+{
+    PL011State* s = opaque;
+
+    /* Sanity-check input state */
+    if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
+        s->read_count > ARRAY_SIZE(s->read_fifo)) {
+        return -1;
+    }
+
+    if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
+        /*
+         * Older versions of PL011 didn't ensure that the single
+         * character in the FIFO in FIFO-disabled mode is in
+         * element 0 of the array; convert to follow the current
+         * code's assumptions.
+         */
+        s->read_fifo[0] = s->read_fifo[s->read_pos];
+        s->read_pos = 0;
+    }
+
+    return 0;
+}
+
 static const VMStateDescription vmstate_pl011 = {
     .name = "pl011",
     .version_id = 2,
     .minimum_version_id = 2,
+    .post_load = pl011_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(readbuff, PL011State),
         VMSTATE_UINT32(flags, PL011State),
-- 
2.34.1



  parent reply	other threads:[~2023-02-03 14:32 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-03 14:28 [PULL 00/33] target-arm queue Peter Maydell
2023-02-03 14:28 ` [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3 Peter Maydell
2023-02-03 14:28 ` [PULL 02/33] target/arm: Fix physical address resolution for Stage2 Peter Maydell
2023-02-03 14:28 ` [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code Peter Maydell
2023-02-03 14:28 ` Peter Maydell [this message]
2023-02-03 14:28 ` [PULL 05/33] hw/char/pl011: implement a reset method Peter Maydell
2023-02-03 14:29 ` [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset Peter Maydell
2023-02-03 14:29 ` [PULL 07/33] hvf: arm: Add support for GICv3 Peter Maydell
2023-02-03 14:29 ` [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic Peter Maydell
2023-02-03 14:29 ` [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit Peter Maydell
2023-02-03 14:29 ` [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus Peter Maydell
2023-02-03 14:29 ` [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Peter Maydell
2023-02-03 14:29 ` [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Peter Maydell
2023-02-03 14:29 ` [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier Peter Maydell
2023-02-03 14:29 ` [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Peter Maydell
2023-02-03 14:29 ` [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Peter Maydell
2023-02-03 14:29 ` [PULL 18/33] target/arm: Define the FEAT_FGT registers Peter Maydell
2023-02-03 14:29 ` [PULL 19/33] target/arm: Implement FGT trapping infrastructure Peter Maydell
2023-02-03 14:29 ` [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Peter Maydell
2023-02-03 14:29 ` [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35 Peter Maydell
2023-02-03 14:29 ` [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 Peter Maydell
2023-02-03 14:29 ` [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Peter Maydell
2023-02-03 14:29 ` [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17 Peter Maydell
2023-02-03 14:29 ` [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47 Peter Maydell
2023-02-03 14:29 ` [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Peter Maydell
2023-02-03 14:29 ` [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap Peter Maydell
2023-02-03 14:29 ` [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Peter Maydell
2023-02-03 14:29 ` [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Peter Maydell
2023-02-03 14:29 ` [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' Peter Maydell
2023-02-03 18:54 ` [PULL 00/33] target-arm queue Peter Maydell

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