From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/33] hw/char/pl011: implement a reset method
Date: Fri, 3 Feb 2023 14:28:59 +0000 [thread overview]
Message-ID: <20230203142927.834793-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org>
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
PL011 currently lacks a reset method. Implement it.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/pl011.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 05e8bdc050e..ca7537d8ed2 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -427,11 +427,6 @@ static void pl011_init(Object *obj)
s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
ClockUpdate);
- s->read_trigger = 1;
- s->ifl = 0x12;
- s->cr = 0x300;
- s->flags = 0x90;
-
s->id = pl011_id_arm;
}
@@ -443,11 +438,32 @@ static void pl011_realize(DeviceState *dev, Error **errp)
pl011_event, NULL, s, NULL, true);
}
+static void pl011_reset(DeviceState *dev)
+{
+ PL011State *s = PL011(dev);
+
+ s->lcr = 0;
+ s->rsr = 0;
+ s->dmacr = 0;
+ s->int_enabled = 0;
+ s->int_level = 0;
+ s->ilpr = 0;
+ s->ibrd = 0;
+ s->fbrd = 0;
+ s->read_pos = 0;
+ s->read_count = 0;
+ s->read_trigger = 1;
+ s->ifl = 0x12;
+ s->cr = 0x300;
+ s->flags = 0x90;
+}
+
static void pl011_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = pl011_realize;
+ dc->reset = pl011_reset;
dc->vmsd = &vmstate_pl011;
device_class_set_props(dc, pl011_properties);
}
--
2.34.1
next prev parent reply other threads:[~2023-02-03 14:37 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 14:28 [PULL 00/33] target-arm queue Peter Maydell
2023-02-03 14:28 ` [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3 Peter Maydell
2023-02-03 14:28 ` [PULL 02/33] target/arm: Fix physical address resolution for Stage2 Peter Maydell
2023-02-03 14:28 ` [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code Peter Maydell
2023-02-03 14:28 ` [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility Peter Maydell
2023-02-03 14:28 ` Peter Maydell [this message]
2023-02-03 14:29 ` [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset Peter Maydell
2023-02-03 14:29 ` [PULL 07/33] hvf: arm: Add support for GICv3 Peter Maydell
2023-02-03 14:29 ` [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic Peter Maydell
2023-02-03 14:29 ` [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit Peter Maydell
2023-02-03 14:29 ` [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus Peter Maydell
2023-02-03 14:29 ` [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Peter Maydell
2023-02-03 14:29 ` [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Peter Maydell
2023-02-03 14:29 ` [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier Peter Maydell
2023-02-03 14:29 ` [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Peter Maydell
2023-02-03 14:29 ` [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Peter Maydell
2023-02-03 14:29 ` [PULL 18/33] target/arm: Define the FEAT_FGT registers Peter Maydell
2023-02-03 14:29 ` [PULL 19/33] target/arm: Implement FGT trapping infrastructure Peter Maydell
2023-02-03 14:29 ` [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Peter Maydell
2023-02-03 14:29 ` [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35 Peter Maydell
2023-02-03 14:29 ` [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 Peter Maydell
2023-02-03 14:29 ` [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Peter Maydell
2023-02-03 14:29 ` [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17 Peter Maydell
2023-02-03 14:29 ` [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47 Peter Maydell
2023-02-03 14:29 ` [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Peter Maydell
2023-02-03 14:29 ` [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap Peter Maydell
2023-02-03 14:29 ` [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Peter Maydell
2023-02-03 14:29 ` [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Peter Maydell
2023-02-03 14:29 ` [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' Peter Maydell
2023-02-03 18:54 ` [PULL 00/33] target-arm queue Peter Maydell
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