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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset
Date: Fri,  3 Feb 2023 14:29:00 +0000	[thread overview]
Message-ID: <20230203142927.834793-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20230203142927.834793-1-peter.maydell@linaro.org>

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index ca7537d8ed2..c15cb7af20b 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -92,6 +92,16 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 }
 
+static inline void pl011_reset_fifo(PL011State *s)
+{
+    s->read_count = 0;
+    s->read_pos = 0;
+
+    /* Reset FIFO flags */
+    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
+    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -239,8 +249,7 @@ static void pl011_write(void *opaque, hwaddr offset,
     case 11: /* UARTLCR_H */
         /* Reset the FIFO state on FIFO enable or disable */
         if ((s->lcr ^ value) & 0x10) {
-            s->read_count = 0;
-            s->read_pos = 0;
+            pl011_reset_fifo(s);
         }
         if ((s->lcr ^ value) & 0x1) {
             int break_enable = value & 0x1;
@@ -450,12 +459,11 @@ static void pl011_reset(DeviceState *dev)
     s->ilpr = 0;
     s->ibrd = 0;
     s->fbrd = 0;
-    s->read_pos = 0;
-    s->read_count = 0;
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
-    s->flags = 0x90;
+    s->flags = 0;
+    pl011_reset_fifo(s);
 }
 
 static void pl011_class_init(ObjectClass *oc, void *data)
-- 
2.34.1



  parent reply	other threads:[~2023-02-03 14:31 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-03 14:28 [PULL 00/33] target-arm queue Peter Maydell
2023-02-03 14:28 ` [PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3 Peter Maydell
2023-02-03 14:28 ` [PULL 02/33] target/arm: Fix physical address resolution for Stage2 Peter Maydell
2023-02-03 14:28 ` [PULL 03/33] hw/char/pl011: refactor FIFO depth handling code Peter Maydell
2023-02-03 14:28 ` [PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility Peter Maydell
2023-02-03 14:28 ` [PULL 05/33] hw/char/pl011: implement a reset method Peter Maydell
2023-02-03 14:29 ` Peter Maydell [this message]
2023-02-03 14:29 ` [PULL 07/33] hvf: arm: Add support for GICv3 Peter Maydell
2023-02-03 14:29 ` [PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic Peter Maydell
2023-02-03 14:29 ` [PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit Peter Maydell
2023-02-03 14:29 ` [PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus Peter Maydell
2023-02-03 14:29 ` [PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly Peter Maydell
2023-02-03 14:29 ` [PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} Peter Maydell
2023-02-03 14:29 ` [PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier Peter Maydell
2023-02-03 14:29 ` [PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps Peter Maydell
2023-02-03 14:29 ` [PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 Peter Maydell
2023-02-03 14:29 ` [PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled Peter Maydell
2023-02-03 14:29 ` [PULL 18/33] target/arm: Define the FEAT_FGT registers Peter Maydell
2023-02-03 14:29 ` [PULL 19/33] target/arm: Implement FGT trapping infrastructure Peter Maydell
2023-02-03 14:29 ` [PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23 Peter Maydell
2023-02-03 14:29 ` [PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35 Peter Maydell
2023-02-03 14:29 ` [PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63 Peter Maydell
2023-02-03 14:29 ` [PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63 Peter Maydell
2023-02-03 14:29 ` [PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11 Peter Maydell
2023-02-03 14:29 ` [PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17 Peter Maydell
2023-02-03 14:29 ` [PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47 Peter Maydell
2023-02-03 14:29 ` [PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63 Peter Maydell
2023-02-03 14:29 ` [PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap Peter Maydell
2023-02-03 14:29 ` [PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps Peter Maydell
2023-02-03 14:29 ` [PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps Peter Maydell
2023-02-03 14:29 ` [PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max' Peter Maydell
2023-02-03 18:54 ` [PULL 00/33] target-arm queue Peter Maydell

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