From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 0/9] target/arm: Housekeeping around NVIC
Date: Mon, 6 Feb 2023 13:17:05 +0100 [thread overview]
Message-ID: <20230206121714.85084-1-philmd@linaro.org> (raw)
Few cleanups while using link properties between CPU/NVIC:
- Restrict code to sysemu|useremu or tcg
- Simplify ID_PFR1 on useremu
- Move NVIC helpersto "hw/intc/armv7m_nvic.h"
Something odd occurs when an ARM CPU is realized, the
CPU reset handler is called, ending calling
armv7m_nvic_neg_prio_requested() on an unrealized NVIC.
I kludged by checking whether the NVIC is realized, but
this rather looks like a code smell...
Philippe Mathieu-Daudé (9):
target/arm: Restrict v7-M MMU helpers to sysemu TCG
target/arm: Constify ID_PFR1 on user emulation
target/arm: Avoid resetting CPUARMState::eabi field
target/arm: Restrict CPUARMState::arm_boot_info to sysemu
target/arm: Restrict CPUARMState::gicv3state to sysemu
target/arm: Restrict CPUARMState::nvic to sysemu and store as
NVICState*
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
hw/intc/armv7m_nvic: Allow calling neg_prio_requested on unrealized
NVIC
hw/arm/armv7m: Pass CPU/NVIC using object_property_add_const_link()
hw/arm/armv7m.c | 4 +-
hw/intc/armv7m_nvic.c | 44 +++++------
include/hw/intc/armv7m_nvic.h | 128 ++++++++++++++++++++++++++++++-
target/arm/cpu.c | 8 +-
target/arm/cpu.h | 137 ++--------------------------------
target/arm/cpu_tcg.c | 3 +
target/arm/helper.c | 14 +++-
target/arm/m_helper.c | 9 ++-
8 files changed, 179 insertions(+), 168 deletions(-)
--
2.38.1
next reply other threads:[~2023-02-06 12:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 12:17 Philippe Mathieu-Daudé [this message]
2023-02-06 12:17 ` [PATCH 1/9] target/arm: Restrict v7-M MMU helpers to sysemu TCG Philippe Mathieu-Daudé
2023-02-06 18:48 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 2/9] target/arm: Constify ID_PFR1 on user emulation Philippe Mathieu-Daudé
2023-02-06 18:38 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 3/9] target/arm: Avoid resetting CPUARMState::eabi field Philippe Mathieu-Daudé
2023-02-06 18:37 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 4/9] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Philippe Mathieu-Daudé
2023-02-06 18:52 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 5/9] target/arm: Restrict CPUARMState::gicv3state " Philippe Mathieu-Daudé
2023-02-06 18:53 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 6/9] target/arm: Restrict CPUARMState::nvic to sysemu and store as NVICState* Philippe Mathieu-Daudé
2023-02-06 18:57 ` Richard Henderson
2023-02-06 19:00 ` Philippe Mathieu-Daudé
2023-02-06 19:17 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 7/9] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' Philippe Mathieu-Daudé
2023-02-06 18:59 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 8/9] hw/intc/armv7m_nvic: Allow calling neg_prio_requested on unrealized NVIC Philippe Mathieu-Daudé
2023-02-06 12:17 ` [PATCH 9/9] hw/arm/armv7m: Pass CPU/NVIC using object_property_add_const_link() Philippe Mathieu-Daudé
2023-02-06 14:35 ` Philippe Mathieu-Daudé
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