From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 3/9] target/arm: Avoid resetting CPUARMState::eabi field
Date: Mon, 6 Feb 2023 13:17:08 +0100 [thread overview]
Message-ID: <20230206121714.85084-4-philmd@linaro.org> (raw)
In-Reply-To: <20230206121714.85084-1-philmd@linaro.org>
Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/cpu.h | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7bc97fece9..bbbcf2e153 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -721,11 +721,6 @@ typedef struct CPUArchState {
ARMVectorReg zarray[ARM_MAX_VQ * 16];
#endif
-#if defined(CONFIG_USER_ONLY)
- /* For usermode syscall translation. */
- int eabi;
-#endif
-
struct CPUBreakpoint *cpu_breakpoint[16];
struct CPUWatchpoint *cpu_watchpoint[16];
@@ -772,6 +767,10 @@ typedef struct CPUArchState {
uint32_t ctrl;
} sau;
+#if defined(CONFIG_USER_ONLY)
+ /* For usermode syscall translation. */
+ int eabi;
+#endif
void *nvic;
const struct arm_boot_info *boot_info;
/* Store GICv3CPUState to access from this struct */
--
2.38.1
next prev parent reply other threads:[~2023-02-06 12:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 12:17 [PATCH 0/9] target/arm: Housekeeping around NVIC Philippe Mathieu-Daudé
2023-02-06 12:17 ` [PATCH 1/9] target/arm: Restrict v7-M MMU helpers to sysemu TCG Philippe Mathieu-Daudé
2023-02-06 18:48 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 2/9] target/arm: Constify ID_PFR1 on user emulation Philippe Mathieu-Daudé
2023-02-06 18:38 ` Richard Henderson
2023-02-06 12:17 ` Philippe Mathieu-Daudé [this message]
2023-02-06 18:37 ` [PATCH 3/9] target/arm: Avoid resetting CPUARMState::eabi field Richard Henderson
2023-02-06 12:17 ` [PATCH 4/9] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Philippe Mathieu-Daudé
2023-02-06 18:52 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 5/9] target/arm: Restrict CPUARMState::gicv3state " Philippe Mathieu-Daudé
2023-02-06 18:53 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 6/9] target/arm: Restrict CPUARMState::nvic to sysemu and store as NVICState* Philippe Mathieu-Daudé
2023-02-06 18:57 ` Richard Henderson
2023-02-06 19:00 ` Philippe Mathieu-Daudé
2023-02-06 19:17 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 7/9] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' Philippe Mathieu-Daudé
2023-02-06 18:59 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 8/9] hw/intc/armv7m_nvic: Allow calling neg_prio_requested on unrealized NVIC Philippe Mathieu-Daudé
2023-02-06 12:17 ` [PATCH 9/9] hw/arm/armv7m: Pass CPU/NVIC using object_property_add_const_link() Philippe Mathieu-Daudé
2023-02-06 14:35 ` Philippe Mathieu-Daudé
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