From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 8/9] hw/intc/armv7m_nvic: Allow calling neg_prio_requested on unrealized NVIC
Date: Mon, 6 Feb 2023 13:17:13 +0100 [thread overview]
Message-ID: <20230206121714.85084-9-philmd@linaro.org> (raw)
In-Reply-To: <20230206121714.85084-1-philmd@linaro.org>
armv7m_nvic_neg_prio_requested() is called via arm_cpu_reset_hold()
during CPU realize() time, when the NVIC isn't yet realized:
(lldb) bt
* frame #0: 0x10059ed5c armv7m_nvic_neg_prio_requested(opaque=0x1180087b0, secure=true) at armv7m_nvic.c:404:9
frame #1: 0x100383018 arm_v7m_mmu_idx_for_secstate [inlined] arm_v7m_mmu_idx_for_secstate_and_priv(...) at m_helper.c:2882:19
frame #2: 0x10038300c arm_v7m_mmu_idx_for_secstate(..., secstate=true) at m_helper.c:2893:12
frame #3: 0x10036e9bc arm_mmu_idx_el(...) at helper.c:11799:16 [artificial]
frame #4: 0x100366cd4 arm_rebuild_hflags [inlined] rebuild_hflags_internal(env=0x118411f30) at helper.c:12129:25
frame #5: 0x100366c18 arm_rebuild_hflags(env=0x118411f30) at helper.c:12142:19
frame #6: 0x10035f1c4 arm_cpu_reset_hold(...) at cpu.c:541:5 [artificial]
frame #7: 0x10066b354 resettable_phase_hold(obj=0x118410000, opaque=0x000000000, ...) at resettable.c:0
frame #8: 0x10066ac40 resettable_assert_reset(obj=0x118410000, ...) at resettable.c:60:5
frame #9: 0x10066ab1c resettable_reset(obj=0x118410000, type=RESET_TYPE_COLD) at resettable.c:45:5
frame #10: 0x100669568 device_cold_reset(...) at qdev.c:255:5 [artificial]
frame #11: 0x10000ca28 cpu_reset(cpu=0x118410000) at cpu-common.c:114:5
frame #12: 0x10035ec74 arm_cpu_realizefn(dev=0x118410000, errp=0x16fdfb910) at cpu.c:2145:5
frame #13: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13
frame #14: 0x100671b98 property_set_bool(obj=0x118410000, ...) at object.c:2285:5
frame #15: 0x10066fdf4 object_property_set(obj=0x118410000, name="realized", ...) at object.c:1420:5
frame #16: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10
frame #17: 0x10067026c object_property_set_bool(...) at object.c:1489:15
frame #18: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial]
frame #19: 0x1003101bc armv7m_realize(dev=0x118008480, ...) at armv7m.c:344:10
frame #20: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13
frame #21: 0x100671b98 property_set_bool(obj=0x118008480, ...) at object.c:2285:5
frame #22: 0x10066fdf4 object_property_set(obj=0x118008480, name="realized", ...) at object.c:1420:5
frame #23: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10
frame #24: 0x10067026c object_property_set_bool(...) at object.c:1489:15
frame #25: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial]
frame #26: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artificial]
frame #27: 0x100350e1c armsse_realize(dev=0x118008150, ...) at armsse.c:1043:14
frame #28: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13
frame #29: 0x100671b98 property_set_bool(obj=0x118008150, ...) at object.c:2285:5
frame #30: 0x10066fdf4 object_property_set(obj=0x118008150, name="realized", ...) at object.c:1420:5
frame #31: 0x100673da8 object_property_set_qobject(...) at qom-qobject.c:28:10
frame #32: 0x10067026c object_property_set_bool(...) at object.c:1489:15
frame #33: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial]
frame #34: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artificial]
frame #35: 0x100349354 mps2tz_common_init(machine=0x118008000) at mps2-tz.c:834:5
frame #36: 0x10008e6b8 machine_run_board_init(machine=0x118008000, ...) at machine.c:1405:5
(lldb) frame select 12
frame #12: 0x10035ec74 arm_cpu_realizefn(dev=0x118410000, errp=0x16fdfb910) at cpu.c:2145:5
2142 }
2143
2144 qemu_init_vcpu(cs);
-> 2145 cpu_reset(cs);
2146
2147 acc->parent_realize(dev, errp);
2148 }
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/intc/armv7m_nvic.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index e54553283f..d9c7e414bc 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -399,6 +399,11 @@ bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
* mean we don't allow FAULTMASK_NS to actually make the execution
* priority negative). Compare pseudocode IsReqExcPriNeg().
*/
+
+ if (!DEVICE(s)->realized) { /* XXX Why are we called while not realized? */
+ return false;
+ }
+
if (s->cpu->env.v7m.faultmask[secure]) {
return true;
}
--
2.38.1
next prev parent reply other threads:[~2023-02-06 12:18 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 12:17 [PATCH 0/9] target/arm: Housekeeping around NVIC Philippe Mathieu-Daudé
2023-02-06 12:17 ` [PATCH 1/9] target/arm: Restrict v7-M MMU helpers to sysemu TCG Philippe Mathieu-Daudé
2023-02-06 18:48 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 2/9] target/arm: Constify ID_PFR1 on user emulation Philippe Mathieu-Daudé
2023-02-06 18:38 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 3/9] target/arm: Avoid resetting CPUARMState::eabi field Philippe Mathieu-Daudé
2023-02-06 18:37 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 4/9] target/arm: Restrict CPUARMState::arm_boot_info to sysemu Philippe Mathieu-Daudé
2023-02-06 18:52 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 5/9] target/arm: Restrict CPUARMState::gicv3state " Philippe Mathieu-Daudé
2023-02-06 18:53 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 6/9] target/arm: Restrict CPUARMState::nvic to sysemu and store as NVICState* Philippe Mathieu-Daudé
2023-02-06 18:57 ` Richard Henderson
2023-02-06 19:00 ` Philippe Mathieu-Daudé
2023-02-06 19:17 ` Richard Henderson
2023-02-06 12:17 ` [PATCH 7/9] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' Philippe Mathieu-Daudé
2023-02-06 18:59 ` Richard Henderson
2023-02-06 12:17 ` Philippe Mathieu-Daudé [this message]
2023-02-06 12:17 ` [PATCH 9/9] hw/arm/armv7m: Pass CPU/NVIC using object_property_add_const_link() Philippe Mathieu-Daudé
2023-02-06 14:35 ` Philippe Mathieu-Daudé
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