From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
Bin Meng <bmeng@tinylab.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 11/32] target/riscv: set tval for triggered watchpoints
Date: Tue, 7 Feb 2023 17:09:22 +1000 [thread overview]
Message-ID: <20230207070943.2558857-12-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20230207070943.2558857-1-alistair.francis@opensource.wdc.com>
From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 ++++++
target/riscv/debug.c | 1 -
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0d72466f3b..ad8d82662c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1639,6 +1639,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
tval = env->bins;
break;
+ case RISCV_EXCP_BREAKPOINT:
+ if (cs->watchpoint_hit) {
+ tval = cs->watchpoint_hit->hitaddr;
+ cs->watchpoint_hit = NULL;
+ }
+ break;
default:
break;
}
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index bf4840a6a3..b091293069 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -761,7 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
if (cs->watchpoint_hit) {
if (cs->watchpoint_hit->flags & BP_CPU) {
- cs->watchpoint_hit = NULL;
do_trigger_action(env, DBG_ACTION_BP);
}
} else {
--
2.39.1
next prev parent reply other threads:[~2023-02-07 7:14 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-07 7:09 [PULL 00/32] riscv-to-apply queue Alistair Francis
2023-02-07 7:09 ` [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw Alistair Francis
2023-02-07 7:09 ` [PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs Alistair Francis
2023-02-07 7:09 ` [PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled Alistair Francis
2023-02-07 7:09 ` [PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes Alistair Francis
2023-02-07 7:09 ` [PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Alistair Francis
2023-02-07 7:09 ` [PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Alistair Francis
2023-02-07 7:09 ` [PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions Alistair Francis
2023-02-07 7:09 ` [PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Alistair Francis
2023-02-07 7:09 ` [PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Alistair Francis
2023-02-07 7:09 ` [PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Alistair Francis
2023-02-07 7:09 ` Alistair Francis [this message]
2023-02-07 7:09 ` [PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack() Alistair Francis
2023-02-07 7:09 ` [PULL 13/32] hw/riscv: split fdt address calculation from fdt load Alistair Francis
2023-02-07 7:09 ` [PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics Alistair Francis
2023-02-07 7:09 ` [PULL 15/32] RISC-V: Adding XTheadCmo ISA extension Alistair Francis
2023-02-07 7:09 ` [PULL 16/32] RISC-V: Adding XTheadSync " Alistair Francis
2023-02-07 7:09 ` [PULL 17/32] RISC-V: Adding XTheadBa " Alistair Francis
2023-02-07 7:09 ` [PULL 18/32] RISC-V: Adding XTheadBb " Alistair Francis
2023-02-07 7:09 ` [PULL 19/32] RISC-V: Adding XTheadBs " Alistair Francis
2023-02-07 7:09 ` [PULL 20/32] RISC-V: Adding XTheadCondMov " Alistair Francis
2023-02-07 7:09 ` [PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions Alistair Francis
2023-02-07 7:09 ` [PULL 22/32] RISC-V: Adding T-Head MemPair extension Alistair Francis
2023-02-07 7:09 ` [PULL 23/32] RISC-V: Adding T-Head MemIdx extension Alistair Francis
2023-02-07 7:09 ` [PULL 24/32] RISC-V: Adding T-Head FMemIdx extension Alistair Francis
2023-02-07 7:09 ` [PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11 Alistair Francis
2023-02-07 7:09 ` [PULL 26/32] RISC-V: Add initial support for T-Head C906 Alistair Francis
2023-02-07 7:09 ` [PULL 27/32] RISC-V: Adding XTheadFmv ISA extension Alistair Francis
2023-02-07 7:09 ` [PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support Alistair Francis
2023-02-07 7:09 ` [PULL 29/32] target/riscv: fix for virtual instr exception Alistair Francis
2023-02-07 7:09 ` [PULL 30/32] target/riscv: fix ctzw behavior Alistair Francis
2023-02-07 7:09 ` [PULL 31/32] target/riscv: fix SBI getchar handler for KVM Alistair Francis
2023-02-07 7:09 ` [PULL 32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint() Alistair Francis
2023-02-07 20:12 ` [PULL 00/32] riscv-to-apply queue Peter Maydell
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