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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=395dd5341=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Christoph M=C3=BCllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/xthead.decode | 3 +++ target/riscv/cpu.c | 2 ++ target/riscv/translate.c | 3 ++- target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index be86c2fb95..876eaebd0e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 = @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 =20 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index def27a53f2..c541924214 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba= ), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb= ), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), @@ -1094,6 +1095,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 387ef0ad8b..880324e617 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,8 @@ static bool always_true_p(DisasContext *ctx __attrib= ute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } =20 #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc index ebfab90dd9..bc1605445d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) =20 +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_t= h_tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } =20 +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ =20 static inline int priv_level(DisasContext *ctx) --=20 2.39.1