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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=395dd5341=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Christoph M=C3=BCllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph M=C3=BCllner Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_vendorid.h | 6 ++++++ target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51"= ) #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34"= ) #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54"= ) +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906"= ) #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu =3D false; } =20 +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RV= U); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g =3D true; + cpu->cfg.ext_c =3D true; + cpu->cfg.ext_u =3D true; + cpu->cfg.ext_s =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.ext_xtheadba =3D true; + cpu->cfg.ext_xtheadbb =3D true; + cpu->cfg.ext_xtheadbs =3D true; + cpu->cfg.ext_xtheadcmo =3D true; + cpu->cfg.ext_xtheadcondmov =3D true; + cpu->cfg.ext_xtheadfmemidx =3D true; + cpu->cfg.ext_xtheadmac =3D true; + cpu->cfg.ext_xtheadmemidx =3D true; + cpu->cfg.ext_xtheadmempair =3D true; + cpu->cfg.ext_xtheadsync =3D true; + + cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; --=20 2.39.1