* [PULL 01/12] target/tricore: Fix OPC2_32_RCRW_IMASK translation
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 02/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK Bastian Koppelmann
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index df9e46c649..8de4e56b1f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RCRW_IMASK:
- tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
+ tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_movi_tl(temp2, (1 << width) - 1);
- tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
+ tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
tcg_gen_movi_tl(temp2, const4);
- tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
+ tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
temp3 = tcg_temp_new();
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 02/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
2023-02-08 9:14 ` [PULL 01/12] target/tricore: Fix OPC2_32_RCRW_IMASK translation Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 03/12] target/tricore: Fix OPC2_32_RCRW_INSERT translation Bastian Koppelmann
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-3-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 7 +++++++
tests/tcg/tricore/test_imask.S | 10 ++++++++++
3 files changed, 18 insertions(+)
create mode 100644 tests/tcg/tricore/test_imask.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 5007c60ce8..bc0cfae8d0 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -10,6 +10,7 @@ TESTS += test_dvstep.tst
TESTS += test_fadd.tst
TESTS += test_fmul.tst
TESTS += test_ftoi.tst
+TESTS += test_imask.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 0d76fc403a..ceb7e9c0b7 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -111,6 +111,13 @@ test_ ## num: \
insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2; \
)
+#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
+ TEST_CASE_E(num, res_lo, res_hi, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2); \
+ )
+
/* Pass/Fail handling part */
#define TEST_PASSFAIL \
j pass; \
diff --git a/tests/tcg/tricore/test_imask.S b/tests/tcg/tricore/test_imask.S
new file mode 100644
index 0000000000..356cf398b8
--- /dev/null
+++ b/tests/tcg/tricore/test_imask.S
@@ -0,0 +1,10 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# res[31:0]
+# insn num res[63:32] | imm1 rs1 imm2
+# | | | | | | |
+ TEST_E_IDI(imask, 1, 0x000f0000, 0x00050000, 0x5, 0x10, 0x4)
+
+ TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 03/12] target/tricore: Fix OPC2_32_RCRW_INSERT translation
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
2023-02-08 9:14 ` [PULL 01/12] target/tricore: Fix OPC2_32_RCRW_IMASK translation Bastian Koppelmann
2023-02-08 9:14 ` [PULL 02/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 04/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT Bastian Koppelmann
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8de4e56b1f..6149d4f5c0 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5805,8 +5805,8 @@ static void decode_rcrw_insert(DisasContext *ctx)
tcg_gen_movi_tl(temp, width);
tcg_gen_movi_tl(temp2, const4);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
- gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_temp_free(temp3);
break;
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 04/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (2 preceding siblings ...)
2023-02-08 9:14 ` [PULL 03/12] target/tricore: Fix OPC2_32_RCRW_INSERT translation Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 05/12] target/tricore: Fix RRPW_DEXTR Bastian Koppelmann
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 16 ++++++++++++----
tests/tcg/tricore/test_insert.S | 9 +++++++++
3 files changed, 22 insertions(+), 4 deletions(-)
create mode 100644 tests/tcg/tricore/test_insert.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index bc0cfae8d0..afabba8631 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -11,6 +11,7 @@ TESTS += test_fadd.tst
TESTS += test_fmul.tst
TESTS += test_ftoi.tst
TESTS += test_imask.tst
+TESTS += test_insert.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index ceb7e9c0b7..4f2bc3cb0f 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -9,10 +9,10 @@
/* Register definitions */
#define DREG_RS1 %d0
#define DREG_RS2 %d1
-#define DREG_RS3 %d4
-#define DREG_CALC_RESULT %d1
-#define DREG_CALC_PSW %d2
-#define DREG_CORRECT_PSW %d3
+#define DREG_RS3 %d2
+#define DREG_CALC_RESULT %d3
+#define DREG_CALC_PSW %d4
+#define DREG_CORRECT_PSW %d5
#define DREG_TEMP_LI %d10
#define DREG_TEMP %d11
#define DREG_TEST_NUM %d14
@@ -103,6 +103,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
)
+#define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/test_insert.S b/tests/tcg/tricore/test_insert.S
new file mode 100644
index 0000000000..d5fd2237e1
--- /dev/null
+++ b/tests/tcg/tricore/test_insert.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 imm1 rs2 imm2
+# | | | | | | |
+ TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
+
+ TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 05/12] target/tricore: Fix RRPW_DEXTR
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (3 preceding siblings ...)
2023-02-08 9:14 ` [PULL 04/12] tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 06/12] tests/tcg/tricore: Add tests for RRPW_DEXTR Bastian Koppelmann
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
if we used const16 == 0 we would crash qemu with the error:
../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed
This whole instruction can be handled by 'tcg_gen_extract2_tl' which
takes care of this special case as well.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-6-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6149d4f5c0..3b4ec530b1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8706,15 +8706,9 @@ static void decode_32Bit_opc(DisasContext *ctx)
r2 = MASK_OP_RRPW_S2(ctx->opcode);
r3 = MASK_OP_RRPW_D(ctx->opcode);
const16 = MASK_OP_RRPW_POS(ctx->opcode);
- if (r1 == r2) {
- tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
- } else {
- temp = tcg_temp_new();
- tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
- tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
- tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
- tcg_temp_free(temp);
- }
+
+ tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1],
+ 32 - const16);
break;
/* RRR Format */
case OPCM_32_RRR_COND_SELECT:
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 06/12] tests/tcg/tricore: Add tests for RRPW_DEXTR
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (4 preceding siblings ...)
2023-02-08 9:14 ` [PULL 05/12] target/tricore: Fix RRPW_DEXTR Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR Bastian Koppelmann
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-7-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 8 +++++
tests/tcg/tricore/test_dextr.S | 40 +++++++++++++++++++++++
3 files changed, 49 insertions(+)
create mode 100644 tests/tcg/tricore/test_dextr.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index afabba8631..e83cc4b7cd 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -6,6 +6,7 @@ ASFLAGS =
TESTS += test_abs.tst
TESTS += test_bmerge.tst
TESTS += test_clz.tst
+TESTS += test_dextr.tst
TESTS += test_dvstep.tst
TESTS += test_fadd.tst
TESTS += test_fmul.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 4f2bc3cb0f..8bc0faf1e4 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -95,6 +95,14 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
)
+#define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm; \
+ )
+
#define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/test_dextr.S b/tests/tcg/tricore/test_dextr.S
new file mode 100644
index 0000000000..c8a9fc453a
--- /dev/null
+++ b/tests/tcg/tricore/test_dextr.S
@@ -0,0 +1,40 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 rs2 imm
+# | | | | | |
+ TEST_D_DDI(dextr, 1, 0xabcdef01, 0xabcdef01, 0x23456789, 0)
+ TEST_D_DDI(dextr, 2, 0x579bde02, 0xabcdef01, 0x23456789, 1)
+ TEST_D_DDI(dextr, 3, 0xaf37bc04, 0xabcdef01, 0x23456789, 2)
+ TEST_D_DDI(dextr, 4, 0x5e6f7809, 0xabcdef01, 0x23456789, 3)
+ TEST_D_DDI(dextr, 5, 0xbcdef012, 0xabcdef01, 0x23456789, 4)
+ TEST_D_DDI(dextr, 6, 0x79bde024, 0xabcdef01, 0x23456789, 5)
+ TEST_D_DDI(dextr, 7, 0xf37bc048, 0xabcdef01, 0x23456789, 6)
+ TEST_D_DDI(dextr, 8, 0xe6f78091, 0xabcdef01, 0x23456789, 7)
+ TEST_D_DDI(dextr, 9, 0xcdef0123, 0xabcdef01, 0x23456789, 8)
+ TEST_D_DDI(dextr, 10, 0x9bde0246, 0xabcdef01, 0x23456789, 9)
+ TEST_D_DDI(dextr, 11, 0x37bc048d, 0xabcdef01, 0x23456789, 10)
+ TEST_D_DDI(dextr, 12, 0x6f78091a, 0xabcdef01, 0x23456789, 11)
+ TEST_D_DDI(dextr, 13, 0xdef01234, 0xabcdef01, 0x23456789, 12)
+ TEST_D_DDI(dextr, 14, 0xbde02468, 0xabcdef01, 0x23456789, 13)
+ TEST_D_DDI(dextr, 15, 0x7bc048d1, 0xabcdef01, 0x23456789, 14)
+ TEST_D_DDI(dextr, 16, 0xf78091a2, 0xabcdef01, 0x23456789, 15)
+ TEST_D_DDI(dextr, 17, 0xef012345, 0xabcdef01, 0x23456789, 16)
+ TEST_D_DDI(dextr, 18, 0xde02468a, 0xabcdef01, 0x23456789, 17)
+ TEST_D_DDI(dextr, 19, 0xbc048d15, 0xabcdef01, 0x23456789, 18)
+ TEST_D_DDI(dextr, 20, 0x78091a2b, 0xabcdef01, 0x23456789, 19)
+ TEST_D_DDI(dextr, 21, 0xf0123456, 0xabcdef01, 0x23456789, 20)
+ TEST_D_DDI(dextr, 22, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
+ TEST_D_DDI(dextr, 23, 0xc048d159, 0xabcdef01, 0x23456789, 22)
+ TEST_D_DDI(dextr, 24, 0x8091a2b3, 0xabcdef01, 0x23456789, 23)
+ TEST_D_DDI(dextr, 25, 0x01234567, 0xabcdef01, 0x23456789, 24)
+ TEST_D_DDI(dextr, 26, 0x02468acf, 0xabcdef01, 0x23456789, 25)
+ TEST_D_DDI(dextr, 27, 0x048d159e, 0xabcdef01, 0x23456789, 26)
+ TEST_D_DDI(dextr, 28, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
+ TEST_D_DDI(dextr, 29, 0x12345678, 0xabcdef01, 0x23456789, 28)
+ TEST_D_DDI(dextr, 30, 0x2468acf1, 0xabcdef01, 0x23456789, 29)
+ TEST_D_DDI(dextr, 31, 0x48d159e2, 0xabcdef01, 0x23456789, 30)
+ TEST_D_DDI(dextr, 32, 0x91a2b3c4, 0xabcdef01, 0x23456789, 31)
+
+ TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (5 preceding siblings ...)
2023-02-08 9:14 ` [PULL 06/12] tests/tcg/tricore: Add tests for RRPW_DEXTR Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 08/12] tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests Bastian Koppelmann
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the
right by 32 which is undefined behaviour. In this case the TriCore would
do nothing an just return the higher register cpu_reg_d[r1]. We fixed
that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower
register.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-8-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3b4ec530b1..8bf78b46d0 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8245,10 +8245,19 @@ static void decode_rrrr_extract_insert(DisasContext *ctx)
if (r1 == r2) {
tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
} else {
+ TCGv msw = tcg_temp_new();
+ TCGv zero = tcg_constant_tl(0);
tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
- tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
- tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
- tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
+ tcg_gen_subfi_tl(msw, 32, tmp_pos);
+ tcg_gen_shr_tl(msw, cpu_gpr_d[r2], msw);
+ /*
+ * if pos == 0, then we do cpu_gpr_d[r2] << 32, which is undefined
+ * behaviour. So check that case here and set the low bits to zero
+ * which effectivly returns cpu_gpr_d[r1]
+ */
+ tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw);
+ tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw);
+ tcg_temp_free(msw);
}
break;
case OPC2_32_RRRR_EXTR:
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 08/12] tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (6 preceding siblings ...)
2023-02-08 9:14 ` [PULL 07/12] target/tricore: Fix OPC2_32_RRRR_DEXTR Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 09/12] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC Bastian Koppelmann
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-9-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/macros.h | 9 +++++++++
tests/tcg/tricore/test_dextr.S | 35 ++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 8bc0faf1e4..06bdbf83cb 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -78,6 +78,15 @@ test_ ## num: \
insn DREG_CORRECT_RESULT, DREG_RS1; \
)
+#define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ LI(DREG_RS3, rs3); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
+ )
+
#define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/test_dextr.S b/tests/tcg/tricore/test_dextr.S
index c8a9fc453a..82c8fe5185 100644
--- a/tests/tcg/tricore/test_dextr.S
+++ b/tests/tcg/tricore/test_dextr.S
@@ -37,4 +37,39 @@ _start:
TEST_D_DDI(dextr, 31, 0x48d159e2, 0xabcdef01, 0x23456789, 30)
TEST_D_DDI(dextr, 32, 0x91a2b3c4, 0xabcdef01, 0x23456789, 31)
+# insn num result rs1 rs2 rs3
+# | | | | | |
+ TEST_D_DDD(dextr, 33, 0xabcdef01, 0xabcdef01, 0x23456789, 0)
+ TEST_D_DDD(dextr, 34, 0x579bde02, 0xabcdef01, 0x23456789, 1)
+ TEST_D_DDD(dextr, 35, 0xaf37bc04, 0xabcdef01, 0x23456789, 2)
+ TEST_D_DDD(dextr, 36, 0x5e6f7809, 0xabcdef01, 0x23456789, 3)
+ TEST_D_DDD(dextr, 37, 0xbcdef012, 0xabcdef01, 0x23456789, 4)
+ TEST_D_DDD(dextr, 38, 0x79bde024, 0xabcdef01, 0x23456789, 5)
+ TEST_D_DDD(dextr, 39, 0xf37bc048, 0xabcdef01, 0x23456789, 6)
+ TEST_D_DDD(dextr, 40, 0xe6f78091, 0xabcdef01, 0x23456789, 7)
+ TEST_D_DDD(dextr, 41, 0xcdef0123, 0xabcdef01, 0x23456789, 8)
+ TEST_D_DDD(dextr, 42, 0x9bde0246, 0xabcdef01, 0x23456789, 9)
+ TEST_D_DDD(dextr, 43, 0x37bc048d, 0xabcdef01, 0x23456789, 10)
+ TEST_D_DDD(dextr, 44, 0x6f78091a, 0xabcdef01, 0x23456789, 11)
+ TEST_D_DDD(dextr, 45, 0xdef01234, 0xabcdef01, 0x23456789, 12)
+ TEST_D_DDD(dextr, 46, 0xbde02468, 0xabcdef01, 0x23456789, 13)
+ TEST_D_DDD(dextr, 47, 0x7bc048d1, 0xabcdef01, 0x23456789, 14)
+ TEST_D_DDD(dextr, 48, 0xf78091a2, 0xabcdef01, 0x23456789, 15)
+ TEST_D_DDD(dextr, 49, 0xef012345, 0xabcdef01, 0x23456789, 16)
+ TEST_D_DDD(dextr, 51, 0xde02468a, 0xabcdef01, 0x23456789, 17)
+ TEST_D_DDD(dextr, 52, 0xbc048d15, 0xabcdef01, 0x23456789, 18)
+ TEST_D_DDD(dextr, 53, 0x78091a2b, 0xabcdef01, 0x23456789, 19)
+ TEST_D_DDD(dextr, 54, 0xf0123456, 0xabcdef01, 0x23456789, 20)
+ TEST_D_DDD(dextr, 55, 0xe02468ac, 0xabcdef01, 0x23456789, 21)
+ TEST_D_DDD(dextr, 56, 0xc048d159, 0xabcdef01, 0x23456789, 22)
+ TEST_D_DDD(dextr, 57, 0x8091a2b3, 0xabcdef01, 0x23456789, 23)
+ TEST_D_DDD(dextr, 58, 0x01234567, 0xabcdef01, 0x23456789, 24)
+ TEST_D_DDD(dextr, 59, 0x02468acf, 0xabcdef01, 0x23456789, 25)
+ TEST_D_DDD(dextr, 60, 0x048d159e, 0xabcdef01, 0x23456789, 26)
+ TEST_D_DDD(dextr, 61, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
+ TEST_D_DDD(dextr, 62, 0x12345678, 0xabcdef01, 0x23456789, 28)
+ TEST_D_DDD(dextr, 63, 0x2468acf1, 0xabcdef01, 0x23456789, 29)
+ TEST_D_DDD(dextr, 64, 0x48d159e2, 0xabcdef01, 0x23456789, 30)
+ TEST_D_DDD(dextr, 65, 0x91a2b3c4, 0xabcdef01, 0x23456789, 31)
+
TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 09/12] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (7 preceding siblings ...)
2023-02-08 9:14 ` [PULL 08/12] tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 10/12] tests/tcg/tricore: Add LD.BU tests Bastian Koppelmann
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Richard Henderson
we were sign extending the result of the load, while the instruction
clearly states that the result should be unsigned.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-10-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8bf78b46d0..ab386cef50 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -4964,7 +4964,7 @@ static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
break;
case OPC2_32_BO_LD_BU_PREINC:
- gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
+ gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
break;
case OPC2_32_BO_LD_D_SHORTOFF:
CHECK_REG_PAIR(r1);
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 10/12] tests/tcg/tricore: Add LD.BU tests
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (8 preceding siblings ...)
2023-02-08 9:14 ` [PULL 09/12] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 11/12] target/tricore: Fix OPC1_16_SRO_LD_H translation Bastian Koppelmann
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-11-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 23 +++++++++++++++++++++++
tests/tcg/tricore/test_ld_bu.S | 15 +++++++++++++++
3 files changed, 39 insertions(+)
create mode 100644 tests/tcg/tricore/test_ld_bu.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index e83cc4b7cd..b6c19dbecd 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -13,6 +13,7 @@ TESTS += test_fmul.tst
TESTS += test_ftoi.tst
TESTS += test_imask.tst
TESTS += test_insert.tst
+TESTS += test_ld_bu.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 06bdbf83cb..109ef62a4d 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -4,6 +4,10 @@
movh DREG_TEMP_LI, up:val; \
or reg, reg, DREG_TEMP_LI; \
+#define LIA(reg, val) \
+ LI(DREG_TEMP, val) \
+ mov.a reg, DREG_TEMP;
+
/* Address definitions */
#define TESTDEV_ADDR 0xf0000000
/* Register definitions */
@@ -18,6 +22,10 @@
#define DREG_TEST_NUM %d14
#define DREG_CORRECT_RESULT %d15
+#define AREG_ADDR %a0
+#define AREG_CORRECT_RESULT %a3
+#define MEM_BASE_ADDR 0xd0000000
+
#define DREG_DEV_ADDR %a15
#define EREG_RS1 %e6
@@ -60,11 +68,24 @@ test_ ## num: \
mov DREG_TEST_NUM, num; \
jne DREG_CALC_PSW, DREG_CORRECT_PSW, fail;
+#define TEST_LD(insn, num, result, addr_result, ld_pattern) \
+test_ ## num: \
+ LIA(AREG_ADDR, test_data) \
+ insn DREG_CALC_RESULT, ld_pattern; \
+ LI(DREG_CORRECT_RESULT, result) \
+ mov DREG_TEST_NUM, num; \
+ jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail; \
+ mov.d DREG_CALC_RESULT, AREG_ADDR; \
+ LI(DREG_CORRECT_RESULT, addr_result) \
+ jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
+
/* Actual test case type
* e.g inst %dX, %dY -> TEST_D_D
* inst %dX, %dY, %dZ -> TEST_D_DD
* inst %eX, %dY, %dZ -> TEST_E_DD
*/
+
+
#define TEST_D_D(insn, num, result, rs1) \
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
@@ -143,6 +164,8 @@ test_ ## num: \
insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2); \
)
+
+
/* Pass/Fail handling part */
#define TEST_PASSFAIL \
j pass; \
diff --git a/tests/tcg/tricore/test_ld_bu.S b/tests/tcg/tricore/test_ld_bu.S
new file mode 100644
index 0000000000..ff9dac128b
--- /dev/null
+++ b/tests/tcg/tricore/test_ld_bu.S
@@ -0,0 +1,15 @@
+#include "macros.h"
+.data
+test_data:
+ .word 0xaffedead
+ .word 0x001122ff
+.text
+.global _start
+_start:
+# expect. addr reg val after load
+# insn num expect. load value | pattern for loading
+# | | | | |
+ TEST_LD(ld.bu, 1, 0xff, MEM_BASE_ADDR + 4, [+AREG_ADDR]4) # pre_inc
+ TEST_LD(ld.bu, 2, 0xad, MEM_BASE_ADDR + 4, [AREG_ADDR+]4) # post_inc
+
+ TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 11/12] target/tricore: Fix OPC1_16_SRO_LD_H translation
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (9 preceding siblings ...)
2023-02-08 9:14 ` [PULL 10/12] tests/tcg/tricore: Add LD.BU tests Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-08 9:14 ` [PULL 12/12] tests/tcg/tricore: Add test for ld.h Bastian Koppelmann
2023-02-09 11:23 ` [PULL 00/12] tricore queue Peter Maydell
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, Anton Kochkov, Philippe Mathieu-Daudé,
Eitan Eliahu
From: Anton Kochkov <anton.kochkov@proton.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Eitan Eliahu <eitan_eliahu@hotmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652
Message-Id: <20230112142258.514079-1-anton.kochkov@proton.me>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ab386cef50..7ac34efd76 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
break;
case OPC1_16_SRO_LD_H:
- gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
+ gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
break;
case OPC1_16_SRO_LD_W:
gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 12/12] tests/tcg/tricore: Add test for ld.h
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (10 preceding siblings ...)
2023-02-08 9:14 ` [PULL 11/12] target/tricore: Fix OPC1_16_SRO_LD_H translation Bastian Koppelmann
@ 2023-02-08 9:14 ` Bastian Koppelmann
2023-02-09 11:23 ` [PULL 00/12] tricore queue Peter Maydell
12 siblings, 0 replies; 14+ messages in thread
From: Bastian Koppelmann @ 2023-02-08 9:14 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
this exercises the error reported in
https://gitlab.com/qemu-project/qemu/-/issues/652.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230203132132.511254-1-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/macros.h | 13 +++++++++++++
tests/tcg/tricore/test_ld_h.S | 15 +++++++++++++++
3 files changed, 29 insertions(+)
create mode 100644 tests/tcg/tricore/test_ld_h.S
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index b6c19dbecd..d2446af8b4 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -14,6 +14,7 @@ TESTS += test_ftoi.tst
TESTS += test_imask.tst
TESTS += test_insert.tst
TESTS += test_ld_bu.tst
+TESTS += test_ld_h.tst
TESTS += test_madd.tst
TESTS += test_msub.tst
TESTS += test_muls.tst
diff --git a/tests/tcg/tricore/macros.h b/tests/tcg/tricore/macros.h
index 109ef62a4d..ec4f5bff52 100644
--- a/tests/tcg/tricore/macros.h
+++ b/tests/tcg/tricore/macros.h
@@ -21,6 +21,7 @@
#define DREG_TEMP %d11
#define DREG_TEST_NUM %d14
#define DREG_CORRECT_RESULT %d15
+#define DREG_CORRECT_RESULT_2 %d13
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
@@ -79,6 +80,18 @@ test_ ## num: \
LI(DREG_CORRECT_RESULT, addr_result) \
jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
+#define TEST_LD_SRO(insn, num, result, addr_result, ld_pattern) \
+test_ ## num: \
+ LIA(AREG_ADDR, test_data) \
+ insn %d15, ld_pattern; \
+ LI(DREG_CORRECT_RESULT_2, result) \
+ mov DREG_TEST_NUM, num; \
+ jne %d15, DREG_CORRECT_RESULT_2, fail; \
+ mov.d DREG_CALC_RESULT, AREG_ADDR; \
+ LI(DREG_CORRECT_RESULT, addr_result) \
+ jne DREG_CALC_RESULT, DREG_CORRECT_RESULT, fail;
+
+
/* Actual test case type
* e.g inst %dX, %dY -> TEST_D_D
* inst %dX, %dY, %dZ -> TEST_D_DD
diff --git a/tests/tcg/tricore/test_ld_h.S b/tests/tcg/tricore/test_ld_h.S
new file mode 100644
index 0000000000..d3c157a046
--- /dev/null
+++ b/tests/tcg/tricore/test_ld_h.S
@@ -0,0 +1,15 @@
+#include "macros.h"
+.data
+test_data:
+ .word 0xaffedead
+ .word 0x001122ff
+.text
+.global _start
+_start:
+# expect. addr reg val after load
+# insn num expect. load value | pattern for loading
+# | | | | |
+ TEST_LD (ld.h, 1, 0xffffaffe, MEM_BASE_ADDR, [AREG_ADDR]2)
+ TEST_LD_SRO(ld.h, 2, 0x000022ff, MEM_BASE_ADDR, [AREG_ADDR]4)
+
+ TEST_PASSFAIL
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PULL 00/12] tricore queue
2023-02-08 9:14 [PULL 00/12] tricore queue Bastian Koppelmann
` (11 preceding siblings ...)
2023-02-08 9:14 ` [PULL 12/12] tests/tcg/tricore: Add test for ld.h Bastian Koppelmann
@ 2023-02-09 11:23 ` Peter Maydell
12 siblings, 0 replies; 14+ messages in thread
From: Peter Maydell @ 2023-02-09 11:23 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: qemu-devel
On Wed, 8 Feb 2023 at 09:14, Bastian Koppelmann
<kbastian@mail.uni-paderborn.de> wrote:
>
> The following changes since commit 969d09c3a6186c0a4bc8a41db0c1aba1c76081fc:
>
> Merge tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu into staging (2023-02-07 20:13:38 +0000)
>
> are available in the Git repository at:
>
> https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230208
>
> for you to fetch changes up to 6e34f54d88184b25db4fbc4dd1665d9be1a9e21c:
>
> tests/tcg/tricore: Add test for ld.h (2023-02-08 10:02:46 +0100)
>
> ----------------------------------------------------------------
> tricore insn bugfixes for qemu 8.0
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 14+ messages in thread