From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>,
qemu-arm@nongnu.org,
"Elena Ufimtseva" <elena.ufimtseva@oracle.com>,
qemu-block@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Ani Sinha" <ani@anisinha.ca>, "John Snow" <jsnow@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Jagannathan Raman" <jag.raman@oracle.com>,
qemu-ppc@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Igor Mammedov" <imammedo@redhat.com>,
"John G Johnson" <john.g.johnson@oracle.com>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v7 09/23] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
Date: Sun, 12 Feb 2023 13:37:51 +0100 [thread overview]
Message-ID: <20230212123805.30799-10-shentey@gmail.com> (raw)
In-Reply-To: <20230212123805.30799-1-shentey@gmail.com>
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221022150508.26830-21-shentey@gmail.com>
---
include/hw/southbridge/piix.h | 5 ++---
hw/isa/piix3.c | 8 ++++----
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index f84a5d15cf..096a85e384 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -31,7 +31,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -43,10 +42,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index dfdae27daf..55835912b8 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -87,7 +87,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -119,7 +119,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
--
2.39.1
next prev parent reply other threads:[~2023-02-12 12:39 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-12 12:37 [PATCH v7 00/23] Consolidate PIIX south bridges Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 01/23] hw/i386/pc: Create RTC controllers in " Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 02/23] hw/i386/pc: No need for rtc_state to be an out-parameter Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 03/23] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 04/23] hw/isa/piix3: Create USB controller in host device Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 05/23] hw/isa/piix3: Create power management " Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 06/23] hw/isa/piix3: Move ISA bus IRQ assignments into " Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 07/23] hw/isa/piix3: Create IDE controller in " Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 08/23] hw/isa/piix3: Wire up ACPI interrupt internally Bernhard Beschow
2023-02-12 12:37 ` Bernhard Beschow [this message]
2023-02-12 12:37 ` [PATCH v7 10/23] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 11/23] hw/isa/piix3: Rename piix3_reset() " Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 12/23] hw/isa/piix3: Drop the "3" from PIIX base class Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 13/23] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 14/23] hw/isa/piix4: Remove unused inbound ISA interrupt lines Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 15/23] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 16/23] hw/isa/piix4: Create the "intr" property during init() already Bernhard Beschow
2023-02-12 12:37 ` [PATCH v7 17/23] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 18/23] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 19/23] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 20/23] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 21/23] hw/isa/piix: Rename functions to be shared for interrupt triggering Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 22/23] hw/isa/piix: Consolidate IRQ triggering Bernhard Beschow
2023-02-12 12:38 ` [PATCH v7 23/23] hw/isa/piix: Share PIIX3's base class with PIIX4 Bernhard Beschow
2023-02-23 17:25 ` [PATCH v7 00/23] Consolidate PIIX south bridges Bernhard Beschow
2023-03-01 22:19 ` Michael S. Tsirkin
2023-03-02 21:25 ` Bernhard Beschow
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230212123805.30799-10-shentey@gmail.com \
--to=shentey@gmail.com \
--cc=ani@anisinha.ca \
--cc=aurelien@aurel32.net \
--cc=eduardo@habkost.net \
--cc=elena.ufimtseva@oracle.com \
--cc=f4bug@amsat.org \
--cc=hpoussin@reactos.org \
--cc=imammedo@redhat.com \
--cc=jag.raman@oracle.com \
--cc=jiaxun.yang@flygoat.com \
--cc=john.g.johnson@oracle.com \
--cc=jsnow@redhat.com \
--cc=kraxel@redhat.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).