From: Bin Meng <bmeng@tinylab.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org
Subject: [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs
Date: Tue, 14 Feb 2023 12:12:48 +0800 [thread overview]
Message-ID: <20230213180215.1524938-16-bmeng@tinylab.org> (raw)
In-Reply-To: <20230213180215.1524938-1-bmeng@tinylab.org>
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
addding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/csr.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d6bcb7f275..c6a7745cb2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -951,6 +951,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -971,11 +984,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
--
2.25.1
next prev parent reply other threads:[~2023-02-14 4:23 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 18:01 [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-13 18:01 ` [PATCH 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-14 8:40 ` weiwei
2023-02-17 2:11 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check() Bin Meng
2023-02-14 8:43 ` weiwei
2023-02-17 2:15 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 03/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-14 8:45 ` weiwei
2023-02-17 2:20 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-02-14 8:46 ` weiwei
2023-02-17 2:23 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 05/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 06/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-14 8:50 ` [PATCH 07/18] target/riscv: Simplify {read,write}_pmpcfg() " weiwei
2023-02-17 2:26 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-14 8:51 ` weiwei
2023-02-17 2:30 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-14 8:56 ` weiwei
2023-02-17 2:36 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-14 9:02 ` weiwei
2023-02-17 2:39 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-14 9:13 ` weiwei
2023-02-17 2:43 ` LIU Zhiwei
2023-02-13 19:19 ` [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Daniel Henrique Barboza
2023-02-14 14:31 ` Bin Meng
2023-02-14 1:09 ` [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-14 9:16 ` weiwei
2023-02-17 2:48 ` LIU Zhiwei
2023-02-14 1:09 ` [PATCH 13/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-14 9:18 ` weiwei
2023-02-17 2:59 ` LIU Zhiwei
2023-02-14 3:06 ` [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-02-14 9:24 ` weiwei
2023-02-14 4:12 ` Bin Meng [this message]
2023-02-14 9:26 ` [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs weiwei
2023-02-14 4:12 ` [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:31 ` [PATCH 17/18] target/riscv: Group all predicate() routines together Bin Meng
2023-02-14 9:27 ` weiwei
2023-02-14 14:27 ` [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate() Bin Meng
2023-02-14 14:59 ` weiwei
2023-02-15 2:22 ` Bin Meng
2023-02-15 2:57 ` weiwei
2023-02-16 16:40 ` Palmer Dabbelt
2023-02-17 1:59 ` Bin Meng
2023-02-17 17:28 ` Palmer Dabbelt
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