From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Date: Tue, 14 Feb 2023 16:38:28 +0800 [thread overview]
Message-ID: <20230214083833.44205-10-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230214083833.44205-1-liweiwei@iscas.ac.cn>
Check for Zve32f/Zve64d can overlap check for F/D
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f7ecf1a68..9b2711b94b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
switch (s->sew) {
case MO_16:
case MO_32:
- return has_ext(s, RVF);
+ return s->cfg_ptr->ext_zve32f;
case MO_64:
- return has_ext(s, RVD);
+ return s->cfg_ptr->ext_zve64d;
default:
return false;
}
@@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
switch (s->sew) {
case MO_8:
case MO_16:
- return has_ext(s, RVF);
+ return s->cfg_ptr->ext_zve32f;
case MO_32:
- return has_ext(s, RVD);
+ return s->cfg_ptr->ext_zve64d;
default:
return false;
}
--
2.25.1
next prev parent reply other threads:[~2023-02-14 8:46 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 8:38 [Patch 00/14] target/riscv: Some updates to float point related extensions Weiwei Li
2023-02-14 8:38 ` [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh Weiwei Li
2023-02-14 12:09 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx Weiwei Li
2023-02-14 12:10 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin Weiwei Li
2023-02-14 12:12 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 04/14] target/riscv: Add cfg properties for Zv* extension Weiwei Li
2023-02-14 12:14 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D Weiwei Li
2023-02-14 13:21 ` Daniel Henrique Barboza
2023-02-14 13:40 ` weiwei
2023-02-14 14:23 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions Weiwei Li
2023-02-14 13:23 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 07/14] target/riscv: Indent fixes in cpu.c Weiwei Li
2023-02-14 13:24 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f Weiwei Li
2023-02-14 13:25 ` Daniel Henrique Barboza
2023-02-14 8:38 ` Weiwei Li [this message]
2023-02-14 13:26 ` [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f Weiwei Li
2023-02-14 13:28 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions Weiwei Li
2023-02-14 13:30 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64 Weiwei Li
2023-02-14 13:33 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Weiwei Li
2023-02-14 13:37 ` Daniel Henrique Barboza
2023-02-14 13:44 ` weiwei
2023-02-14 8:38 ` [Patch 14/14] target/riscv: Expose properties for Zv* extension Weiwei Li
2023-02-14 13:39 ` Daniel Henrique Barboza
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