[Patch 00/14] target/riscv: Some updates to float point related extensions

[Patch 00/14] target/riscv: Some updates to float point related extensions

[Weiwei Li]

This patchset fixes some relationship for half-precise float point related extensions and vector related extensions. It also adds support for Zvhf{min} and Zve64d extensions.

Specification for Zv* extensions can be found in:

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zvfh-upstream

Weiwei Li (14):
  target/riscv: Fix the relationship between Zfhmin and Zfh
  target/riscv: Fix the relationship between Zhinxmin and Zhinx
  target/riscv: Simplify the check for Zfhmin and Zhinxmin
  target/riscv: Add cfg properties for Zv* extension
  target/riscv: Fix relationship between V, Zve*, F and  D
  target/riscv: Add propertie check for Zvfh{min} extensions
  target/riscv: Indent fixes in cpu.c
  target/riscv: Simplify check for Zve32f and Zve64f
  target/riscv: Replace check for F/D to Zve32f/Zve64d in
    trans_rvv.c.inc
  target/riscv: Remove rebundunt check for zve32f and zve64f
  target/riscv: Add support for Zvfh/zvfhmin extensions
  target/riscv: Fix check for vectore load/store instructions when
    EEW=64
  target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
  target/riscv: Expose properties for Zv* extension

 target/riscv/cpu.c                        |  99 ++++++++----
 target/riscv/cpu.h                        |   3 +
 target/riscv/insn_trans/trans_rvv.c.inc   | 184 +++++++---------------
 target/riscv/insn_trans/trans_rvzfh.c.inc |  25 ++-
 4 files changed, 144 insertions(+), 167 deletions(-)

-- 
2.25.1

[Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh

[Weiwei Li]

Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..eb0cd12a6a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
+    if (cpu->cfg.ext_zfh) {
+        cpu->cfg.ext_zfhmin = true;
+    }
+
+    if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
         error_setg(errp, "Zfh/Zfhmin extensions require F extension");
         return;
     }
-- 
2.25.1

Re: [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dd2f0c753..eb0cd12a6a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> -    if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
> +    if (cpu->cfg.ext_zfh) {
> +        cpu->cfg.ext_zfhmin = true;
> +    }
> +
> +    if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
>           error_setg(errp, "Zfh/Zfhmin extensions require F extension");
>           return;
>       }

[Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx

[Weiwei Li]

Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb0cd12a6a..9a89bea2a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     /* Set the ISA extensions, checks should have happened above */
-    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
-        cpu->cfg.ext_zhinxmin) {
+    if (cpu->cfg.ext_zhinx) {
+        cpu->cfg.ext_zhinxmin = true;
+    }
+
+    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
         cpu->cfg.ext_zfinx = true;
     }
 
-- 
2.25.1

Re: [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
> will be enabled when Zhinx is enabled
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eb0cd12a6a..9a89bea2a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -754,8 +754,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>       }
>   
>       /* Set the ISA extensions, checks should have happened above */
> -    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> -        cpu->cfg.ext_zhinxmin) {
> +    if (cpu->cfg.ext_zhinx) {
> +        cpu->cfg.ext_zhinxmin = true;
> +    }
> +
> +    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
>           cpu->cfg.ext_zfinx = true;
>       }
>   

[Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin

[Weiwei Li]

We needn't check Zfh and Zhinx in these instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++++++++++------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 2ad5716312..85fc1aa822 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -28,15 +28,14 @@
     }                                  \
 } while (0)
 
-#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do {       \
-    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
+#define REQUIRE_ZFHMIN(ctx) do {              \
+    if (!ctx->cfg_ptr->ext_zfhmin) {          \
         return false;                         \
     }                                         \
 } while (0)
 
-#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
-    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin ||          \
-          ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) {     \
+#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do {                 \
+    if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
         return false;                                        \
     }                                                        \
 } while (0)
@@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
     TCGv t0;
 
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);
 
     decode_save_opc(ctx);
     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
     TCGv t0;
 
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);
 
     decode_save_opc(ctx);
     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
 static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
 
     TCGv_i64 dest = dest_fpr(ctx, a->rd);
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
 static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
     REQUIRE_ZDINX_OR_D(ctx);
 
     TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
 static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
 
     TCGv_i64 dest = dest_fpr(ctx, a->rd);
     TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
@@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
 static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
+    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
     REQUIRE_ZDINX_OR_D(ctx);
 
     TCGv_i64 dest = dest_fpr(ctx, a->rd);
@@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
 static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);
 
     TCGv dest = dest_gpr(ctx, a->rd);
 
@@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
 static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
 {
     REQUIRE_FPU;
-    REQUIRE_ZFH_OR_ZFHMIN(ctx);
+    REQUIRE_ZFHMIN(ctx);
 
     TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
 
-- 
2.25.1

Re: [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> We needn't check Zfh and Zhinx in these instructions

Nit: missing period in the end.

> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++++++++++------------
>   1 file changed, 12 insertions(+), 13 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 2ad5716312..85fc1aa822 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -28,15 +28,14 @@
>       }                                  \
>   } while (0)
>   
> -#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do {       \
> -    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
> +#define REQUIRE_ZFHMIN(ctx) do {              \
> +    if (!ctx->cfg_ptr->ext_zfhmin) {          \
>           return false;                         \
>       }                                         \
>   } while (0)
>   
> -#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
> -    if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin ||          \
> -          ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) {     \
> +#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do {                 \
> +    if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
>           return false;                                        \
>       }                                                        \
>   } while (0)
> @@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
>       TCGv t0;
>   
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN(ctx);
> +    REQUIRE_ZFHMIN(ctx);
>   
>       decode_save_opc(ctx);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
>       TCGv t0;
>   
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN(ctx);
> +    REQUIRE_ZFHMIN(ctx);
>   
>       decode_save_opc(ctx);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> @@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
>   static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
> +    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
>   
>       TCGv_i64 dest = dest_fpr(ctx, a->rd);
>       TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
> @@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
>   static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
> +    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
>       REQUIRE_ZDINX_OR_D(ctx);
>   
>       TCGv_i64 dest = dest_fpr(ctx, a->rd);
> @@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
>   static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
> +    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
>   
>       TCGv_i64 dest = dest_fpr(ctx, a->rd);
>       TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
> @@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
>   static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
> +    REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
>       REQUIRE_ZDINX_OR_D(ctx);
>   
>       TCGv_i64 dest = dest_fpr(ctx, a->rd);
> @@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
>   static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN(ctx);
> +    REQUIRE_ZFHMIN(ctx);
>   
>       TCGv dest = dest_gpr(ctx, a->rd);
>   
> @@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
>   static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
>   {
>       REQUIRE_FPU;
> -    REQUIRE_ZFH_OR_ZFHMIN(ctx);
> +    REQUIRE_ZFHMIN(ctx);
>   
>       TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
>   

[Patch 04/14] target/riscv: Add cfg properties for Zv* extension

[Weiwei Li]

Add properties for Zve64d,Zvfh,Zvfhmin extension

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..54c6875617 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -462,7 +462,10 @@ struct RISCVCPUConfig {
     bool ext_zhinxmin;
     bool ext_zve32f;
     bool ext_zve64f;
+    bool ext_zve64d;
     bool ext_zmmul;
+    bool ext_zvfh;
+    bool ext_zvfhmin;
     bool ext_smaia;
     bool ext_ssaia;
     bool ext_sscofpmf;
-- 
2.25.1

Re: [Patch 04/14] target/riscv: Add cfg properties for Zv* extension

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Add properties for Zve64d,Zvfh,Zvfhmin extension

"for Zve64d,Zvfh,Zvfhmin extensions."

> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7128438d8e..54c6875617 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -462,7 +462,10 @@ struct RISCVCPUConfig {
>       bool ext_zhinxmin;
>       bool ext_zve32f;
>       bool ext_zve64f;
> +    bool ext_zve64d;
>       bool ext_zmmul;
> +    bool ext_zvfh;
> +    bool ext_zvfhmin;
>       bool ext_smaia;
>       bool ext_ssaia;
>       bool ext_sscofpmf;

[Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D

[Weiwei Li]

Add dependence chain:
*  V => Zve64d => Zve64f => Zve32f => F
*  V => Zve64d => D

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9a89bea2a3..4797ef9c42 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
-        error_setg(errp, "V extension requires D extension");
+    /* The V vector extension depends on the Zve64d extension */
+    if (cpu->cfg.ext_v) {
+        cpu->cfg.ext_zve64d = true;
+    }
+
+    /* The Zve64d extension depends on the Zve64f extension */
+    if (cpu->cfg.ext_zve64d) {
+        cpu->cfg.ext_zve64f = true;
+    }
+
+    /* The Zve64f extension depends on the Zve32f extension */
+    if (cpu->cfg.ext_zve64f) {
+        cpu->cfg.ext_zve32f = true;
+    }
+
+    if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
+        error_setg(errp, "Zve64d extensions require D extension");
         return;
     }
 
-    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+    if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
         error_setg(errp, "Zve32f/Zve64f extensions require F extension");
         return;
     }
-- 
2.25.1

Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Add dependence chain:
> *  V => Zve64d => Zve64f => Zve32f => F
> *  V => Zve64d => D
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/cpu.c | 21 ++++++++++++++++++---
>   1 file changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9a89bea2a3..4797ef9c42 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> -    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
> -        error_setg(errp, "V extension requires D extension");
> +    /* The V vector extension depends on the Zve64d extension */
> +    if (cpu->cfg.ext_v) {
> +        cpu->cfg.ext_zve64d = true;
> +    }
> +
> +    /* The Zve64d extension depends on the Zve64f extension */
> +    if (cpu->cfg.ext_zve64d) {
> +        cpu->cfg.ext_zve64f = true;
> +    }
> +
> +    /* The Zve64f extension depends on the Zve32f extension */
> +    if (cpu->cfg.ext_zve64f) {
> +        cpu->cfg.ext_zve32f = true;
> +    }
> +
> +    if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
> +        error_setg(errp, "Zve64d extensions require D extension");
>           return;

I'll be honest and confess that I wrote a short essay about the problems I have
with this code. I gave up because in the end it's all stuff that we've been doing
for a long time in riscv_cpu_validate_set_extensions(). I'll see if I can work in
a redesign of that function and in how we're setting extensions automatically
without checking user input and so on.

For now I'll say that this error message seems weird because Zve64d was set to true
without user input. So this ends up happening:

$ ./qemu-system-riscv64 -M virt -cpu rv64,v=true,d=false
qemu-system-riscv64: Zve64d extensions require D extension

It's weird because the user didn't enabled Zve64d but the error message is complaining
about it. Given that the root cause is that ext_v was set, and then we've set other
extensions under the hood, a saner error message in this case would be "V extension
requires D extension".


Thanks,


Daniel



>       }
>   
> -    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
> +    if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
>           error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>           return;
>       }

Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D

[weiwei]

On 2023/2/14 21:21, Daniel Henrique Barboza wrote:
>
>
> On 2/14/23 05:38, Weiwei Li wrote:
>> Add dependence chain:
>> *  V => Zve64d => Zve64f => Zve32f => F
>> *  V => Zve64d => D
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/cpu.c | 21 ++++++++++++++++++---
>>   1 file changed, 18 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 9a89bea2a3..4797ef9c42 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -743,12 +743,27 @@ static void 
>> riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>>           return;
>>       }
>>   -    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
>> -        error_setg(errp, "V extension requires D extension");
>> +    /* The V vector extension depends on the Zve64d extension */
>> +    if (cpu->cfg.ext_v) {
>> +        cpu->cfg.ext_zve64d = true;
>> +    }
>> +
>> +    /* The Zve64d extension depends on the Zve64f extension */
>> +    if (cpu->cfg.ext_zve64d) {
>> +        cpu->cfg.ext_zve64f = true;
>> +    }
>> +
>> +    /* The Zve64f extension depends on the Zve32f extension */
>> +    if (cpu->cfg.ext_zve64f) {
>> +        cpu->cfg.ext_zve32f = true;
>> +    }
>> +
>> +    if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
>> +        error_setg(errp, "Zve64d extensions require D extension");
>>           return;
>
> I'll be honest and confess that I wrote a short essay about the 
> problems I have
> with this code. I gave up because in the end it's all stuff that we've 
> been doing
> for a long time in riscv_cpu_validate_set_extensions(). I'll see if I 
> can work in
> a redesign of that function and in how we're setting extensions 
> automatically
> without checking user input and so on.
>
> For now I'll say that this error message seems weird because Zve64d 
> was set to true
> without user input. So this ends up happening:
>
> $ ./qemu-system-riscv64 -M virt -cpu rv64,v=true,d=false
> qemu-system-riscv64: Zve64d extensions require D extension
>
> It's weird because the user didn't enabled Zve64d but the error 
> message is complaining
> about it. Given that the root cause is that ext_v was set, and then 
> we've set other
> extensions under the hood, a saner error message in this case would be 
> "V extension
> requires D extension".
>
>
> Thanks,
>
>
> Daniel

Thanks for your comments.

V extension depends on Zve64d(which is actually parts of V). So Zve64d 
will be enabled when V is enabled.

And in fact, only the instructions in the Zve64d part of V require D 
extension.

To make it more readable, maybe it can be change to :

"Zve64d (or V) extension requires D extension"

Regards,

Weiwei Li

>
>
>
>>       }
>>   -    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && 
>> !cpu->cfg.ext_f) {
>> +    if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
>>           error_setg(errp, "Zve32f/Zve64f extensions require F 
>> extension");
>>           return;
>>       }

Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D

[Daniel Henrique Barboza]

On 2/14/23 10:40, weiwei wrote:
> 
> On 2023/2/14 21:21, Daniel Henrique Barboza wrote:
>>
>>
>> On 2/14/23 05:38, Weiwei Li wrote:
>>> Add dependence chain:
>>> *  V => Zve64d => Zve64f => Zve32f => F
>>> *  V => Zve64d => D
>>>
>>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>>> ---
>>>   target/riscv/cpu.c | 21 ++++++++++++++++++---
>>>   1 file changed, 18 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index 9a89bea2a3..4797ef9c42 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -743,12 +743,27 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>>>           return;
>>>       }
>>>   -    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
>>> -        error_setg(errp, "V extension requires D extension");
>>> +    /* The V vector extension depends on the Zve64d extension */
>>> +    if (cpu->cfg.ext_v) {
>>> +        cpu->cfg.ext_zve64d = true;
>>> +    }
>>> +
>>> +    /* The Zve64d extension depends on the Zve64f extension */
>>> +    if (cpu->cfg.ext_zve64d) {
>>> +        cpu->cfg.ext_zve64f = true;
>>> +    }
>>> +
>>> +    /* The Zve64f extension depends on the Zve32f extension */
>>> +    if (cpu->cfg.ext_zve64f) {
>>> +        cpu->cfg.ext_zve32f = true;
>>> +    }
>>> +
>>> +    if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
>>> +        error_setg(errp, "Zve64d extensions require D extension");
>>>           return;
>>
>> I'll be honest and confess that I wrote a short essay about the problems I have
>> with this code. I gave up because in the end it's all stuff that we've been doing
>> for a long time in riscv_cpu_validate_set_extensions(). I'll see if I can work in
>> a redesign of that function and in how we're setting extensions automatically
>> without checking user input and so on.
>>
>> For now I'll say that this error message seems weird because Zve64d was set to true
>> without user input. So this ends up happening:
>>
>> $ ./qemu-system-riscv64 -M virt -cpu rv64,v=true,d=false
>> qemu-system-riscv64: Zve64d extensions require D extension
>>
>> It's weird because the user didn't enabled Zve64d but the error message is complaining
>> about it. Given that the root cause is that ext_v was set, and then we've set other
>> extensions under the hood, a saner error message in this case would be "V extension
>> requires D extension".
>>
>>
>> Thanks,
>>
>>
>> Daniel
> 
> Thanks for your comments.
> 
> V extension depends on Zve64d(which is actually parts of V). So Zve64d will be enabled when V is enabled.
> 
> And in fact, only the instructions in the Zve64d part of V require D extension.
> 
> To make it more readable, maybe it can be change to :
> 
> "Zve64d (or V) extension requires D extension"


Yes, that looks better to me. Thanks,


Daniel

> 
> Regards,
> 
> Weiwei Li
> 
>>
>>
>>
>>>       }
>>>   -    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
>>> +    if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
>>>           error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>>>           return;
>>>       }
> 

[Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions

[Weiwei Li]

Add check for Zvfh and Zvfhmin

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4797ef9c42..8fe76707a0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if (cpu->cfg.ext_zvfh) {
+        cpu->cfg.ext_zvfhmin = true;
+    }
+
+    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+        return;
+    }
+
     /* Set the ISA extensions, checks should have happened above */
     if (cpu->cfg.ext_zhinx) {
         cpu->cfg.ext_zhinxmin = true;
-- 
2.25.1

Re: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Add check for Zvfh and Zvfhmin
> 

Nit: Missing period in the end.

> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4797ef9c42..8fe76707a0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           return;
>       }
>   
> +    if (cpu->cfg.ext_zvfh) {
> +        cpu->cfg.ext_zvfhmin = true;
> +    }
> +
> +    if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
> +        error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
> +        return;
> +    }
> +
> +    if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
> +        error_setg(errp, "Zvfh extensions requires Zfhmin extension");
> +        return;
> +    }
> +
>       /* Set the ISA extensions, checks should have happened above */
>       if (cpu->cfg.ext_zhinx) {
>           cpu->cfg.ext_zhinxmin = true;

[Patch 07/14] target/riscv: Indent fixes in cpu.c

[Weiwei Li]

Fix indent problems in vector related check

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8fe76707a0..73711d392d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -798,7 +798,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         }
         if (cpu->cfg.ext_f) {
             error_setg(errp,
-                "Zfinx cannot be supported together with F extension");
+                       "Zfinx cannot be supported together with F extension");
             return;
         }
     }
@@ -861,40 +861,40 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         ext |= RVV;
         if (!is_power_of_2(cpu->cfg.vlen)) {
             error_setg(errp,
-                    "Vector extension VLEN must be power of 2");
+                       "Vector extension VLEN must be power of 2");
             return;
         }
         if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
             error_setg(errp,
-                    "Vector extension implementation only supports VLEN "
-                    "in the range [128, %d]", RV_VLEN_MAX);
+                       "Vector extension implementation only supports VLEN "
+                       "in the range [128, %d]", RV_VLEN_MAX);
             return;
         }
         if (!is_power_of_2(cpu->cfg.elen)) {
             error_setg(errp,
-                    "Vector extension ELEN must be power of 2");
+                       "Vector extension ELEN must be power of 2");
             return;
         }
-    if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
-        error_setg(errp,
-                "Vector extension implementation only supports ELEN "
-                "in the range [8, 64]");
-        return;
-    }
-    if (cpu->cfg.vext_spec) {
-        if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
-            vext_version = VEXT_VERSION_1_00_0;
-        } else {
+        if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
             error_setg(errp,
-                   "Unsupported vector spec version '%s'",
-                   cpu->cfg.vext_spec);
+                       "Vector extension implementation only supports ELEN "
+                       "in the range [8, 64]");
             return;
         }
-    } else {
-        qemu_log("vector version is not specified, "
-                 "use the default value v1.0\n");
-    }
-    set_vext_version(env, vext_version);
+        if (cpu->cfg.vext_spec) {
+            if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+                vext_version = VEXT_VERSION_1_00_0;
+            } else {
+                error_setg(errp,
+                           "Unsupported vector spec version '%s'",
+                           cpu->cfg.vext_spec);
+                return;
+            }
+        } else {
+            qemu_log("vector version is not specified, "
+                     "use the default value v1.0\n");
+        }
+        set_vext_version(env, vext_version);
     }
     if (cpu->cfg.ext_j) {
         ext |= RVJ;
-- 
2.25.1

Re: [Patch 07/14] target/riscv: Indent fixes in cpu.c

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Fix indent problems in vector related check
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 44 ++++++++++++++++++++++----------------------
>   1 file changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8fe76707a0..73711d392d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -798,7 +798,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           }
>           if (cpu->cfg.ext_f) {
>               error_setg(errp,
> -                "Zfinx cannot be supported together with F extension");
> +                       "Zfinx cannot be supported together with F extension");
>               return;
>           }
>       }
> @@ -861,40 +861,40 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>           ext |= RVV;
>           if (!is_power_of_2(cpu->cfg.vlen)) {
>               error_setg(errp,
> -                    "Vector extension VLEN must be power of 2");
> +                       "Vector extension VLEN must be power of 2");
>               return;
>           }
>           if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
>               error_setg(errp,
> -                    "Vector extension implementation only supports VLEN "
> -                    "in the range [128, %d]", RV_VLEN_MAX);
> +                       "Vector extension implementation only supports VLEN "
> +                       "in the range [128, %d]", RV_VLEN_MAX);
>               return;
>           }
>           if (!is_power_of_2(cpu->cfg.elen)) {
>               error_setg(errp,
> -                    "Vector extension ELEN must be power of 2");
> +                       "Vector extension ELEN must be power of 2");
>               return;
>           }
> -    if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
> -        error_setg(errp,
> -                "Vector extension implementation only supports ELEN "
> -                "in the range [8, 64]");
> -        return;
> -    }
> -    if (cpu->cfg.vext_spec) {
> -        if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
> -            vext_version = VEXT_VERSION_1_00_0;
> -        } else {
> +        if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
>               error_setg(errp,
> -                   "Unsupported vector spec version '%s'",
> -                   cpu->cfg.vext_spec);
> +                       "Vector extension implementation only supports ELEN "
> +                       "in the range [8, 64]");
>               return;
>           }
> -    } else {
> -        qemu_log("vector version is not specified, "
> -                 "use the default value v1.0\n");
> -    }
> -    set_vext_version(env, vext_version);
> +        if (cpu->cfg.vext_spec) {
> +            if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
> +                vext_version = VEXT_VERSION_1_00_0;
> +            } else {
> +                error_setg(errp,
> +                           "Unsupported vector spec version '%s'",
> +                           cpu->cfg.vext_spec);
> +                return;
> +            }
> +        } else {
> +            qemu_log("vector version is not specified, "
> +                     "use the default value v1.0\n");
> +        }
> +        set_vext_version(env, vext_version);
>       }
>       if (cpu->cfg.ext_j) {
>           ext |= RVJ;

[Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f

[Weiwei Li]

Zve64f depends on Zve32f, so we can only check Zve32f
in these cases

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index bbb5c3a7b5..6f7ecf1a68 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
         return false;
     }
 
@@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) ||
-        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
-          s->cfg_ptr->ext_zve64f)) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
         return false;
     }
 
-- 
2.25.1

Re: [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Zve64f depends on Zve32f, so we can only check Zve32f
> in these cases
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 8 ++------
>   1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index bbb5c3a7b5..6f7ecf1a68 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -173,9 +173,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>   {
>       TCGv s1, dst;
>   
> -    if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
> -          s->cfg_ptr->ext_zve64f)) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>           return false;
>       }
>   
> @@ -210,9 +208,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
>   {
>       TCGv dst;
>   
> -    if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
> -          s->cfg_ptr->ext_zve64f)) {
> +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
>           return false;
>       }
>   

[Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

[Weiwei Li]

Check for Zve32f/Zve64d can overlap check for F/D

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f7ecf1a68..9b2711b94b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
     switch (s->sew) {
     case MO_16:
     case MO_32:
-        return has_ext(s, RVF);
+        return s->cfg_ptr->ext_zve32f;
     case MO_64:
-        return has_ext(s, RVD);
+        return s->cfg_ptr->ext_zve64d;
     default:
         return false;
     }
@@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
     switch (s->sew) {
     case MO_8:
     case MO_16:
-        return has_ext(s, RVF);
+        return s->cfg_ptr->ext_zve32f;
     case MO_32:
-        return has_ext(s, RVD);
+        return s->cfg_ptr->ext_zve64d;
     default:
         return false;
     }
-- 
2.25.1

Re: [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Check for Zve32f/Zve64d can overlap check for F/D
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 6f7ecf1a68..9b2711b94b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
>       switch (s->sew) {
>       case MO_16:
>       case MO_32:
> -        return has_ext(s, RVF);
> +        return s->cfg_ptr->ext_zve32f;
>       case MO_64:
> -        return has_ext(s, RVD);
> +        return s->cfg_ptr->ext_zve64d;
>       default:
>           return false;
>       }
> @@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
>       switch (s->sew) {
>       case MO_8:
>       case MO_16:
> -        return has_ext(s, RVF);
> +        return s->cfg_ptr->ext_zve32f;
>       case MO_32:
> -        return has_ext(s, RVD);
> +        return s->cfg_ptr->ext_zve64d;
>       default:
>           return false;
>       }

[Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f

[Weiwei Li]

Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 128 ++++--------------------
 1 file changed, 21 insertions(+), 107 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9b2711b94b..9053759546 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -66,50 +66,6 @@ static bool require_scale_rvf(DisasContext *s)
     }
 }
 
-static bool require_zve32f(DisasContext *s)
-{
-    /* RVV + Zve32f = RVV. */
-    if (has_ext(s, RVV)) {
-        return true;
-    }
-
-    /* Zve32f doesn't support FP64. (Section 18.2) */
-    return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
-}
-
-static bool require_scale_zve32f(DisasContext *s)
-{
-    /* RVV + Zve32f = RVV. */
-    if (has_ext(s, RVV)) {
-        return true;
-    }
-
-    /* Zve32f doesn't support FP64. (Section 18.2) */
-    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
-}
-
-static bool require_zve64f(DisasContext *s)
-{
-    /* RVV + Zve64f = RVV. */
-    if (has_ext(s, RVV)) {
-        return true;
-    }
-
-    /* Zve64f doesn't support FP64. (Section 18.2) */
-    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
-}
-
-static bool require_scale_zve64f(DisasContext *s)
-{
-    /* RVV + Zve64f = RVV. */
-    if (has_ext(s, RVV)) {
-        return true;
-    }
-
-    /* Zve64f doesn't support FP64. (Section 18.2) */
-    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
-}
-
 /* Destination vector register group cannot overlap source mask register. */
 static bool require_vm(int vm, int vd)
 {
@@ -2331,9 +2287,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 /* OPFVV without GVEC IR */
@@ -2421,9 +2375,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           vext_check_ss(s, a->rd, a->rs2, a->vm);
 }
 
 /* OPFVF without GVEC IR */
@@ -2461,9 +2413,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 /* OPFVV with WIDEN */
@@ -2506,9 +2456,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
 
 /* OPFVF with WIDEN */
@@ -2540,9 +2488,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
 /* WIDEN OPFVV with WIDEN */
@@ -2585,9 +2531,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
-           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
 
 /* WIDEN OPFVF with WIDEN */
@@ -2664,9 +2608,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV instructions ignore vs1 check */
-           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           vext_check_ss(s, a->rd, a->rs2, a->vm);
 }
 
 static bool do_opfv(DisasContext *s, arg_rmr *a,
@@ -2731,9 +2673,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           vext_check_mss(s, a->rd, a->rs1, a->rs2);
 }
 
 GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2746,9 +2686,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ms(s, a->rd, a->rs2) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           vext_check_ms(s, a->rd, a->rs2);
 }
 
 GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2769,9 +2707,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
     if (require_rvv(s) &&
         require_rvf(s) &&
         vext_check_isa_ill(s) &&
-        require_align(a->rd, s->lmul) &&
-        require_zve32f(s) &&
-        require_zve64f(s)) {
+        require_align(a->rd, s->lmul)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         TCGv_i64 t1;
@@ -2856,18 +2792,14 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_rvf(s) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           require_rvf(s);
 }
 
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           (s->sew != MO_8);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -2918,9 +2850,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
-           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
 
 #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
@@ -2975,18 +2905,14 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           (s->sew != MO_64) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           (s->sew != MO_64);
 }
 
 static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           (s->sew != MO_8);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -3035,9 +2961,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
            require_scale_rvf(s) &&
            vext_check_isa_ill(s) &&
            /* OPFV narrowing instructions ignore vs1 check */
-           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
-           require_scale_zve32f(s) &&
-           require_scale_zve64f(s);
+           vext_check_sd(s, a->rd, a->rs2, a->vm);
 }
 
 #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
@@ -3111,9 +3035,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
 static bool freduction_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_check(s, a) &&
-           require_rvf(s) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           require_rvf(s);
 }
 
 GEN_OPFVV_TRANS(vfredusum_vs, freduction_check)
@@ -3540,9 +3462,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s) &&
-        require_zve32f(s) &&
-        require_zve64f(s)) {
+        vext_check_isa_ill(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         unsigned int ofs = (8 << s->sew);
@@ -3568,9 +3488,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
 {
     if (require_rvv(s) &&
         require_rvf(s) &&
-        vext_check_isa_ill(s) &&
-        require_zve32f(s) &&
-        require_zve64f(s)) {
+        vext_check_isa_ill(s)) {
         gen_set_rm(s, RISCV_FRM_DYN);
 
         /* The instructions ignore LMUL and vector register group. */
@@ -3621,17 +3539,13 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
 static bool fslideup_check(DisasContext *s, arg_rmrr *a)
 {
     return slideup_check(s, a) &&
-           require_rvf(s) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           require_rvf(s);
 }
 
 static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
 {
     return slidedown_check(s, a) &&
-           require_rvf(s) &&
-           require_zve32f(s) &&
-           require_zve64f(s);
+           require_rvf(s);
 }
 
 GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
-- 
2.25.1

Re: [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f

[Daniel Henrique Barboza]

Nit: I believe you mean "redundant" in the title ^

On 2/14/23 05:38, Weiwei Li wrote:
> Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 128 ++++--------------------
>   1 file changed, 21 insertions(+), 107 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9b2711b94b..9053759546 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -66,50 +66,6 @@ static bool require_scale_rvf(DisasContext *s)
>       }
>   }
>   
> -static bool require_zve32f(DisasContext *s)
> -{
> -    /* RVV + Zve32f = RVV. */
> -    if (has_ext(s, RVV)) {
> -        return true;
> -    }
> -
> -    /* Zve32f doesn't support FP64. (Section 18.2) */
> -    return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
> -}
> -
> -static bool require_scale_zve32f(DisasContext *s)
> -{
> -    /* RVV + Zve32f = RVV. */
> -    if (has_ext(s, RVV)) {
> -        return true;
> -    }
> -
> -    /* Zve32f doesn't support FP64. (Section 18.2) */
> -    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
> -}
> -
> -static bool require_zve64f(DisasContext *s)
> -{
> -    /* RVV + Zve64f = RVV. */
> -    if (has_ext(s, RVV)) {
> -        return true;
> -    }
> -
> -    /* Zve64f doesn't support FP64. (Section 18.2) */
> -    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
> -}
> -
> -static bool require_scale_zve64f(DisasContext *s)
> -{
> -    /* RVV + Zve64f = RVV. */
> -    if (has_ext(s, RVV)) {
> -        return true;
> -    }
> -
> -    /* Zve64f doesn't support FP64. (Section 18.2) */
> -    return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
> -}
> -
>   /* Destination vector register group cannot overlap source mask register. */
>   static bool require_vm(int vm, int vd)
>   {
> @@ -2331,9 +2287,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   /* OPFVV without GVEC IR */
> @@ -2421,9 +2375,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           vext_check_ss(s, a->rd, a->rs2, a->vm);
>   }
>   
>   /* OPFVF without GVEC IR */
> @@ -2461,9 +2413,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
>              require_scale_rvf(s) &&
>              (s->sew != MO_8) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   /* OPFVV with WIDEN */
> @@ -2506,9 +2456,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
>              require_scale_rvf(s) &&
>              (s->sew != MO_8) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_ds(s, a->rd, a->rs2, a->vm);
>   }
>   
>   /* OPFVF with WIDEN */
> @@ -2540,9 +2488,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
>              require_scale_rvf(s) &&
>              (s->sew != MO_8) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
>   /* WIDEN OPFVV with WIDEN */
> @@ -2585,9 +2531,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
>              require_scale_rvf(s) &&
>              (s->sew != MO_8) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_dd(s, a->rd, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_dd(s, a->rd, a->rs2, a->vm);
>   }
>   
>   /* WIDEN OPFVF with WIDEN */
> @@ -2664,9 +2608,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
>              /* OPFV instructions ignore vs1 check */
> -           vext_check_ss(s, a->rd, a->rs2, a->vm) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           vext_check_ss(s, a->rd, a->rs2, a->vm);
>   }
>   
>   static bool do_opfv(DisasContext *s, arg_rmr *a,
> @@ -2731,9 +2673,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           vext_check_mss(s, a->rd, a->rs1, a->rs2);
>   }
>   
>   GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
> @@ -2746,9 +2686,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
>       return require_rvv(s) &&
>              require_rvf(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ms(s, a->rd, a->rs2) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           vext_check_ms(s, a->rd, a->rs2);
>   }
>   
>   GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
> @@ -2769,9 +2707,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
>       if (require_rvv(s) &&
>           require_rvf(s) &&
>           vext_check_isa_ill(s) &&
> -        require_align(a->rd, s->lmul) &&
> -        require_zve32f(s) &&
> -        require_zve64f(s)) {
> +        require_align(a->rd, s->lmul)) {
>           gen_set_rm(s, RISCV_FRM_DYN);
>   
>           TCGv_i64 t1;
> @@ -2856,18 +2792,14 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
>   static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_widen_check(s, a) &&
> -           require_rvf(s) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           require_rvf(s);
>   }
>   
>   static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_widen_check(s, a) &&
>              require_scale_rvf(s) &&
> -           (s->sew != MO_8) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           (s->sew != MO_8);
>   }
>   
>   #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
> @@ -2918,9 +2850,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
>              require_scale_rvf(s) &&
>              vext_check_isa_ill(s) &&
>              /* OPFV widening instructions ignore vs1 check */
> -           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_ds(s, a->rd, a->rs2, a->vm);
>   }
>   
>   #define GEN_OPFXV_WIDEN_TRANS(NAME)                                \
> @@ -2975,18 +2905,14 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_narrow_check(s, a) &&
>              require_rvf(s) &&
> -           (s->sew != MO_64) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           (s->sew != MO_64);
>   }
>   
>   static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_narrow_check(s, a) &&
>              require_scale_rvf(s) &&
> -           (s->sew != MO_8) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           (s->sew != MO_8);
>   }
>   
>   #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
> @@ -3035,9 +2961,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
>              require_scale_rvf(s) &&
>              vext_check_isa_ill(s) &&
>              /* OPFV narrowing instructions ignore vs1 check */
> -           vext_check_sd(s, a->rd, a->rs2, a->vm) &&
> -           require_scale_zve32f(s) &&
> -           require_scale_zve64f(s);
> +           vext_check_sd(s, a->rd, a->rs2, a->vm);
>   }
>   
>   #define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM)                  \
> @@ -3111,9 +3035,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
>   static bool freduction_check(DisasContext *s, arg_rmrr *a)
>   {
>       return reduction_check(s, a) &&
> -           require_rvf(s) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           require_rvf(s);
>   }
>   
>   GEN_OPFVV_TRANS(vfredusum_vs, freduction_check)
> @@ -3540,9 +3462,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
>   {
>       if (require_rvv(s) &&
>           require_rvf(s) &&
> -        vext_check_isa_ill(s) &&
> -        require_zve32f(s) &&
> -        require_zve64f(s)) {
> +        vext_check_isa_ill(s)) {
>           gen_set_rm(s, RISCV_FRM_DYN);
>   
>           unsigned int ofs = (8 << s->sew);
> @@ -3568,9 +3488,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
>   {
>       if (require_rvv(s) &&
>           require_rvf(s) &&
> -        vext_check_isa_ill(s) &&
> -        require_zve32f(s) &&
> -        require_zve64f(s)) {
> +        vext_check_isa_ill(s)) {
>           gen_set_rm(s, RISCV_FRM_DYN);
>   
>           /* The instructions ignore LMUL and vector register group. */
> @@ -3621,17 +3539,13 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
>   static bool fslideup_check(DisasContext *s, arg_rmrr *a)
>   {
>       return slideup_check(s, a) &&
> -           require_rvf(s) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           require_rvf(s);
>   }
>   
>   static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
>   {
>       return slidedown_check(s, a) &&
> -           require_rvf(s) &&
> -           require_zve32f(s) &&
> -           require_zve64f(s);
> +           require_rvf(s);
>   }
>   
>   GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)

[Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions

[Weiwei Li]

Zvfh supports vector float point instuctions with SEW = 16
and supports conversions between 8-bit integers adn binary16 values

Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 31 +++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9053759546..9b2c5c9ac0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s)
 
     switch (s->sew) {
     case MO_16:
+        return s->cfg_ptr->ext_zvfh;
     case MO_32:
         return s->cfg_ptr->ext_zve32f;
     case MO_64:
@@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s)
 
     switch (s->sew) {
     case MO_8:
+        return s->cfg_ptr->ext_zvfh;
+    case MO_16:
+        return s->cfg_ptr->ext_zve32f;
+    case MO_32:
+        return s->cfg_ptr->ext_zve64d;
+    default:
+        return false;
+    }
+}
+
+static bool require_scale_rvfmin(DisasContext *s)
+{
+    if (s->mstatus_fs == 0) {
+        return false;
+    }
+
+    switch (s->sew) {
+    case MO_8:
+        return s->cfg_ptr->ext_zvfhmin;
     case MO_16:
         return s->cfg_ptr->ext_zve32f;
     case MO_32:
@@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
-           require_scale_rvf(s) &&
+           require_scale_rvfmin(s) &&
            (s->sew != MO_8);
 }
 
@@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
 }
 
 static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+    return opfv_narrow_check(s, a) &&
+           require_scale_rvfmin(s) &&
+           (s->sew != MO_8);
+}
+
+static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
@@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w,
 GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
                       RISCV_FRM_DYN)
 /* Reuse the helper function from vfncvt.f.f.w */
-GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
                       RISCV_FRM_ROD)
 
 static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
-- 
2.25.1

Re: [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Zvfh supports vector float point instuctions with SEW = 16

s/instuctions/instructions

> and supports conversions between 8-bit integers adn binary16 values

s/adn/and

> 
> Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>   target/riscv/insn_trans/trans_rvv.c.inc | 31 +++++++++++++++++++++++--
>   1 file changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9053759546..9b2c5c9ac0 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s)
>   
>       switch (s->sew) {
>       case MO_16:
> +        return s->cfg_ptr->ext_zvfh;
>       case MO_32:
>           return s->cfg_ptr->ext_zve32f;
>       case MO_64:
> @@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s)
>   
>       switch (s->sew) {
>       case MO_8:
> +        return s->cfg_ptr->ext_zvfh;
> +    case MO_16:
> +        return s->cfg_ptr->ext_zve32f;
> +    case MO_32:
> +        return s->cfg_ptr->ext_zve64d;
> +    default:
> +        return false;
> +    }
> +}
> +
> +static bool require_scale_rvfmin(DisasContext *s)
> +{
> +    if (s->mstatus_fs == 0) {
> +        return false;
> +    }
> +
> +    switch (s->sew) {
> +    case MO_8:
> +        return s->cfg_ptr->ext_zvfhmin;
>       case MO_16:
>           return s->cfg_ptr->ext_zve32f;
>       case MO_32:
> @@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
>   static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_widen_check(s, a) &&
> -           require_scale_rvf(s) &&
> +           require_scale_rvfmin(s) &&
>              (s->sew != MO_8);
>   }
>   
> @@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
>   }
>   
>   static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
> +{
> +    return opfv_narrow_check(s, a) &&
> +           require_scale_rvfmin(s) &&
> +           (s->sew != MO_8);
> +}
> +
> +static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
>   {
>       return opfv_narrow_check(s, a) &&
>              require_scale_rvf(s) &&
> @@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w,
>   GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
>                         RISCV_FRM_DYN)
>   /* Reuse the helper function from vfncvt.f.f.w */
> -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
> +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
>                         RISCV_FRM_ROD)
>   
>   static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)

[Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64

[Weiwei Li]

The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32
(Section 18.3)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9b2c5c9ac0..5dbdce073b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
                require_nf(vd, nf, s->lmul);
 
     /*
-     * All Zve* extensions support all vector load and store instructions,
-     * except Zve64* extensions do not support EEW=64 for index values
-     * when XLEN=32. (Section 18.2)
+     * V extension supports all vector load and store instructions,
+     * except V extension does not support EEW=64 for index values
+     * when XLEN=32. (Section 18.3)
      */
     if (get_xl(s) == MXL_RV32) {
-        ret &= (!has_ext(s, RVV) &&
-                s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
+        ret &= (eew != MO_64);
     }
 
     return ret;
-- 
2.25.1

Re: [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64

[Daniel Henrique Barboza]

Nit in the title: I believe you meant vector. "Vettore" would be fine too.

On 2/14/23 05:38, Weiwei Li wrote:
> The V extension supports all vector load and store instructions except
> the V extension does not support EEW=64 for index values when XLEN=32
> (Section 18.3)
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++-----
>   1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 9b2c5c9ac0..5dbdce073b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
>                  require_nf(vd, nf, s->lmul);
>   
>       /*
> -     * All Zve* extensions support all vector load and store instructions,
> -     * except Zve64* extensions do not support EEW=64 for index values
> -     * when XLEN=32. (Section 18.2)
> +     * V extension supports all vector load and store instructions,
> +     * except V extension does not support EEW=64 for index values
> +     * when XLEN=32. (Section 18.3)
>        */
>       if (get_xl(s) == MXL_RV32) {
> -        ret &= (!has_ext(s, RVV) &&
> -                s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
> +        ret &= (eew != MO_64);
>       }
>   
>       return ret;

[Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

[Weiwei Li]

Only V extension support EEW = 64 in these case: Zve64* extensions
don't support EEW = 64 as commented

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dbdce073b..fc0d0d60e8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
      * are not included for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
 }
 
 static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
@@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
      * are not included for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
 }
 
 GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
@@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
      * for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
 }
 
 static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
@@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
      * for EEW=64 in Zve64*. (Section 18.2)
      */
     return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
 }
 
 GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
-- 
2.25.1

Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Only V extension support EEW = 64 in these case: Zve64* extensions
> don't support EEW = 64 as commented

"as commented" where? In the previous patch?


> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

The code LGTM.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>   target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
>   1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5dbdce073b..fc0d0d60e8 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>        */
>       return opivv_check(s, a) &&
> -           (!has_ext(s, RVV) &&
> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>   }
>   
>   static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
> @@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>        */
>       return opivx_check(s, a) &&
> -           (!has_ext(s, RVV) &&
> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>   }
>   
>   GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
> @@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
>        * for EEW=64 in Zve64*. (Section 18.2)
>        */
>       return opivv_check(s, a) &&
> -           (!has_ext(s, RVV) &&
> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>   }
>   
>   static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
> @@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
>        * for EEW=64 in Zve64*. (Section 18.2)
>        */
>       return opivx_check(s, a) &&
> -           (!has_ext(s, RVV) &&
> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>   }
>   
>   GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)

Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

[weiwei]

On 2023/2/14 21:37, Daniel Henrique Barboza wrote:
>
>
> On 2/14/23 05:38, Weiwei Li wrote:
>> Only V extension support EEW = 64 in these case: Zve64* extensions
>> don't support EEW = 64 as commented
>
> "as commented" where? In the previous patch?
>
>
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>
> The code LGTM.
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
>
>>   target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
>>   1 file changed, 4 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 5dbdce073b..fc0d0d60e8 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>>        */
".... are not included for EEW=64 in Zve64*. (Section 18.2) "

The comment is here, and similar comments can be found in following code.

Regards,

Weiwei Li

>>       return opivv_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
>> @@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * are not included for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivx_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)
>> @@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivv_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
>> @@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>        * for EEW=64 in Zve64*. (Section 18.2)
>>        */
>>       return opivx_check(s, a) &&
>> -           (!has_ext(s, RVV) &&
>> -            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
>> +           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
>>   }
>>     GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)

[Patch 14/14] target/riscv: Expose properties for Zv* extension

[Weiwei Li]

Expose Zve64d,Zvfh,Zvfhmin properties

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 73711d392d..2c71e22ea9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -101,6 +101,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
     ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
     ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
+    ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
+    ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
+    ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
     ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
     ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
@@ -1126,6 +1129,7 @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
+    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
@@ -1185,6 +1189,9 @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
     DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
 
+    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
+    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
+
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.25.1

Re: [Patch 14/14] target/riscv: Expose properties for Zv* extension

[Daniel Henrique Barboza]

On 2/14/23 05:38, Weiwei Li wrote:
> Expose Zve64d,Zvfh,Zvfhmin properties
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>   target/riscv/cpu.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 73711d392d..2c71e22ea9 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -101,6 +101,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
>       ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
>       ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
> +    ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
> +    ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
> +    ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
>       ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
>       ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
>       ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
> @@ -1126,6 +1129,7 @@ static Property riscv_cpu_extensions[] = {
>       DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
>       DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
>       DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> +    DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
>       DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>       DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>       DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
> @@ -1185,6 +1189,9 @@ static Property riscv_cpu_extensions[] = {
>       DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
>       DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
>   
> +    DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
> +    DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
> +
>       DEFINE_PROP_END_OF_LIST(),
>   };
>