From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions
Date: Tue, 14 Feb 2023 16:38:25 +0800 [thread overview]
Message-ID: <20230214083833.44205-7-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230214083833.44205-1-liweiwei@iscas.ac.cn>
Add check for Zvfh and Zvfhmin
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4797ef9c42..8fe76707a0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (cpu->cfg.ext_zvfh) {
+ cpu->cfg.ext_zvfhmin = true;
+ }
+
+ if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
+ error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
+ error_setg(errp, "Zvfh extensions requires Zfhmin extension");
+ return;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
cpu->cfg.ext_zhinxmin = true;
--
2.25.1
next prev parent reply other threads:[~2023-02-14 8:39 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 8:38 [Patch 00/14] target/riscv: Some updates to float point related extensions Weiwei Li
2023-02-14 8:38 ` [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh Weiwei Li
2023-02-14 12:09 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx Weiwei Li
2023-02-14 12:10 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin Weiwei Li
2023-02-14 12:12 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 04/14] target/riscv: Add cfg properties for Zv* extension Weiwei Li
2023-02-14 12:14 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D Weiwei Li
2023-02-14 13:21 ` Daniel Henrique Barboza
2023-02-14 13:40 ` weiwei
2023-02-14 14:23 ` Daniel Henrique Barboza
2023-02-14 8:38 ` Weiwei Li [this message]
2023-02-14 13:23 ` [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 07/14] target/riscv: Indent fixes in cpu.c Weiwei Li
2023-02-14 13:24 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f Weiwei Li
2023-02-14 13:25 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Weiwei Li
2023-02-14 13:26 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f Weiwei Li
2023-02-14 13:28 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions Weiwei Li
2023-02-14 13:30 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64 Weiwei Li
2023-02-14 13:33 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Weiwei Li
2023-02-14 13:37 ` Daniel Henrique Barboza
2023-02-14 13:44 ` weiwei
2023-02-14 8:38 ` [Patch 14/14] target/riscv: Expose properties for Zv* extension Weiwei Li
2023-02-14 13:39 ` Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230214083833.44205-7-liweiwei@iscas.ac.cn \
--to=liweiwei@iscas.ac.cn \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=lazyparser@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=wangjunqiang@iscas.ac.cn \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).