From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [Patch 07/14] target/riscv: Indent fixes in cpu.c
Date: Tue, 14 Feb 2023 16:38:26 +0800 [thread overview]
Message-ID: <20230214083833.44205-8-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230214083833.44205-1-liweiwei@iscas.ac.cn>
Fix indent problems in vector related check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 44 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8fe76707a0..73711d392d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -798,7 +798,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
if (cpu->cfg.ext_f) {
error_setg(errp,
- "Zfinx cannot be supported together with F extension");
+ "Zfinx cannot be supported together with F extension");
return;
}
}
@@ -861,40 +861,40 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
ext |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
- "Vector extension VLEN must be power of 2");
+ "Vector extension VLEN must be power of 2");
return;
}
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
error_setg(errp,
- "Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
+ "Vector extension implementation only supports VLEN "
+ "in the range [128, %d]", RV_VLEN_MAX);
return;
}
if (!is_power_of_2(cpu->cfg.elen)) {
error_setg(errp,
- "Vector extension ELEN must be power of 2");
+ "Vector extension ELEN must be power of 2");
return;
}
- if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
- error_setg(errp,
- "Vector extension implementation only supports ELEN "
- "in the range [8, 64]");
- return;
- }
- if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
- vext_version = VEXT_VERSION_1_00_0;
- } else {
+ if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
+ "Vector extension implementation only supports ELEN "
+ "in the range [8, 64]");
return;
}
- } else {
- qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
- }
- set_vext_version(env, vext_version);
+ if (cpu->cfg.vext_spec) {
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
+ } else {
+ error_setg(errp,
+ "Unsupported vector spec version '%s'",
+ cpu->cfg.vext_spec);
+ return;
+ }
+ } else {
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
+ }
+ set_vext_version(env, vext_version);
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
--
2.25.1
next prev parent reply other threads:[~2023-02-14 8:39 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 8:38 [Patch 00/14] target/riscv: Some updates to float point related extensions Weiwei Li
2023-02-14 8:38 ` [Patch 01/14] target/riscv: Fix the relationship between Zfhmin and Zfh Weiwei Li
2023-02-14 12:09 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 02/14] target/riscv: Fix the relationship between Zhinxmin and Zhinx Weiwei Li
2023-02-14 12:10 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 03/14] target/riscv: Simplify the check for Zfhmin and Zhinxmin Weiwei Li
2023-02-14 12:12 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 04/14] target/riscv: Add cfg properties for Zv* extension Weiwei Li
2023-02-14 12:14 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D Weiwei Li
2023-02-14 13:21 ` Daniel Henrique Barboza
2023-02-14 13:40 ` weiwei
2023-02-14 14:23 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 06/14] target/riscv: Add propertie check for Zvfh{min} extensions Weiwei Li
2023-02-14 13:23 ` Daniel Henrique Barboza
2023-02-14 8:38 ` Weiwei Li [this message]
2023-02-14 13:24 ` [Patch 07/14] target/riscv: Indent fixes in cpu.c Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 08/14] target/riscv: Simplify check for Zve32f and Zve64f Weiwei Li
2023-02-14 13:25 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 09/14] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Weiwei Li
2023-02-14 13:26 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 10/14] target/riscv: Remove rebundunt check for zve32f and zve64f Weiwei Li
2023-02-14 13:28 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 11/14] target/riscv: Add support for Zvfh/zvfhmin extensions Weiwei Li
2023-02-14 13:30 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 12/14] target/riscv: Fix check for vectore load/store instructions when EEW=64 Weiwei Li
2023-02-14 13:33 ` Daniel Henrique Barboza
2023-02-14 8:38 ` [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Weiwei Li
2023-02-14 13:37 ` Daniel Henrique Barboza
2023-02-14 13:44 ` weiwei
2023-02-14 8:38 ` [Patch 14/14] target/riscv: Expose properties for Zv* extension Weiwei Li
2023-02-14 13:39 ` Daniel Henrique Barboza
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