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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id b4-20020a5d4d84000000b002c5621263e3sm4584083wru.19.2023.02.15.05.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 05:45:42 -0800 (PST) Date: Wed, 15 Feb 2023 14:45:41 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com Subject: Re: [PATCH v2 00/11] enable write_misa() and RISCV_FEATURE_* cleanups Message-ID: <20230215134541.hxaspacyttcytod5@orel> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Feb 14, 2023 at 04:23:45PM -0300, Daniel Henrique Barboza wrote: > Hi, > > This new version contains suggestions made by Weiwei Li in v1. Most > notable change is patch 4 from v1, moving up to patch 2 now, to allow > the riscv_cpu_cfg() helper to be used in the MISA CSR patch. > > > Changes in v2: > - former patch 4 moved to patch 2 > - patch 3 (former 2): > - use riscv_cpu_cfg() > - patch 9: > - remove the uneeded RISCVCPUConfig and access mmu via > cpu_cfg->cfg.mmu > - v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg02780.html > > Daniel Henrique Barboza (11): > target/riscv: do not mask unsupported QEMU extensions in write_misa() > target/riscv: introduce riscv_cpu_cfg() > target/riscv: allow users to actually write the MISA CSR > target/riscv: remove RISCV_FEATURE_MISA > target/riscv: remove RISCV_FEATURE_DEBUG > target/riscv/cpu.c: error out if EPMP is enabled without PMP > target/riscv: remove RISCV_FEATURE_EPMP > target/riscv: remove RISCV_FEATURE_PMP > hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in > create_fdt_socket_cpus() > target/riscv: remove RISCV_FEATURE_MMU > target/riscv/cpu: remove CPUArchState::features and friends > > hw/riscv/virt.c | 7 ++++--- > target/riscv/cpu.c | 20 +++++--------------- > target/riscv/cpu.h | 29 ++++++----------------------- > target/riscv/cpu_helper.c | 6 +++--- > target/riscv/csr.c | 15 ++++++--------- > target/riscv/machine.c | 11 ++++------- > target/riscv/monitor.c | 2 +- > target/riscv/op_helper.c | 2 +- > target/riscv/pmp.c | 8 ++++---- > 9 files changed, 34 insertions(+), 66 deletions(-) > > -- > 2.39.1 > > For the series Reviewed-by: Andrew Jones