From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 17/30] tcg/aarch64: Detect have_lse, have_lse2 for linux
Date: Wed, 15 Feb 2023 16:57:26 -1000 [thread overview]
Message-ID: <20230216025739.1211680-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230216025739.1211680-1-richard.henderson@linaro.org>
Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 3 +++
tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index c0b0f614ba..3c0b0d312d 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -57,6 +57,9 @@ typedef enum {
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
+extern bool have_lse;
+extern bool have_lse2;
+
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 05123cce35..d144d1a769 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -13,6 +13,9 @@
#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "qemu/bitops.h"
+#ifdef __linux__
+#include <asm/hwcap.h>
+#endif
/* We're going to re-use TCGType in setting of the SF bit, which controls
the size of the operation performed. If we know the values match, it
@@ -71,6 +74,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
return TCG_REG_X0 + slot;
}
+bool have_lse;
+bool have_lse2;
+
#define TCG_REG_TMP TCG_REG_X30
#define TCG_VEC_TMP TCG_REG_V31
@@ -2912,6 +2918,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
static void tcg_target_init(TCGContext *s)
{
+#ifdef __linux__
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+ have_lse = hwcap & HWCAP_ATOMICS;
+ have_lse2 = hwcap & HWCAP_USCAT;
+#endif
+
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
--
2.34.1
next prev parent reply other threads:[~2023-02-16 2:58 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 2:57 [PATCH v2 00/30] tcg: Improve atomicity support Richard Henderson
2023-02-16 2:57 ` [PATCH v2 01/30] include/qemu/cpuid: Introduce xgetbv_low Richard Henderson
2023-02-16 2:57 ` [PATCH v2 02/30] include/exec/memop: Add bits describing atomicity Richard Henderson
2023-02-28 17:56 ` Alex Bennée
2023-03-15 17:13 ` Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 03/30] accel/tcg: Add cpu_in_serial_context Richard Henderson
2023-02-28 17:57 ` Alex Bennée
2023-03-15 16:07 ` Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 04/30] accel/tcg: Introduce tlb_read_idx Richard Henderson
2023-02-28 17:59 ` Alex Bennée
2023-02-16 2:57 ` [PATCH v2 05/30] accel/tcg: Reorg system mode load helpers Richard Henderson
2023-02-28 18:08 ` Alex Bennée
2023-02-16 2:57 ` [PATCH v2 06/30] accel/tcg: Reorg system mode store helpers Richard Henderson
2023-02-16 2:57 ` [PATCH v2 07/30] accel/tcg: Honor atomicity of loads Richard Henderson
2023-02-28 18:19 ` Alex Bennée
2023-02-16 2:57 ` [PATCH v2 08/30] accel/tcg: Honor atomicity of stores Richard Henderson
2023-02-16 2:57 ` [PATCH v2 09/30] tcg/tci: Use cpu_{ld,st}_mmu Richard Henderson
2023-02-16 2:57 ` [PATCH v2 10/30] tcg: Unify helper_{be,le}_{ld,st}* Richard Henderson
2023-02-16 2:57 ` [PATCH v2 11/30] accel/tcg: Implement helper_{ld, st}*_mmu for user-only Richard Henderson
2023-02-16 2:57 ` [PATCH v2 12/30] tcg: Add 128-bit guest memory primitives Richard Henderson
2023-02-16 2:57 ` [PATCH v2 13/30] meson: Detect atomic128 support with optimization Richard Henderson
2023-02-16 2:57 ` [PATCH v2 14/30] tcg/i386: Add have_atomic16 Richard Henderson
2023-03-15 17:06 ` Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc Richard Henderson
2023-02-16 2:57 ` [PATCH v2 16/30] accel/tcg: Add aarch64 specific support in ldst_atomicity Richard Henderson
2023-02-16 2:57 ` Richard Henderson [this message]
2023-03-15 17:00 ` [PATCH v2 17/30] tcg/aarch64: Detect have_lse, have_lse2 for linux Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 18/30] tcg/aarch64: Detect have_lse, have_lse2 for darwin Richard Henderson
2023-03-15 16:59 ` Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 19/30] accel/tcg: Add have_lse2 support in ldst_atomicity Richard Henderson
2023-02-16 2:57 ` [PATCH v2 20/30] tcg: Introduce TCG_OPF_TYPE_MASK Richard Henderson
2023-02-16 2:57 ` [PATCH v2 21/30] tcg: Add INDEX_op_qemu_{ld,st}_i128 Richard Henderson
2023-02-16 2:57 ` [PATCH v2 22/30] tcg/i386: Introduce tcg_out_mov2 Richard Henderson
2023-02-16 2:57 ` [PATCH v2 23/30] tcg/i386: Introduce tcg_out_testi Richard Henderson
2023-02-16 2:57 ` [PATCH v2 24/30] tcg/i386: Use full load/store helpers in user-only mode Richard Henderson
2023-02-16 2:57 ` [PATCH v2 25/30] tcg/i386: Replace is64 with type in qemu_ld/st routines Richard Henderson
2023-02-16 2:57 ` [PATCH v2 26/30] tcg/i386: Mark Win64 call-saved vector regs as reserved Richard Henderson
2023-02-16 2:57 ` [PATCH v2 27/30] tcg/i386: Examine MemOp for atomicity and alignment Richard Henderson
2023-02-16 2:57 ` [PATCH v2 28/30] tcg/i386: Support 128-bit load/store with have_atomic16 Richard Henderson
2023-02-16 2:57 ` [PATCH v2 29/30] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool Richard Henderson
2023-03-15 16:43 ` Philippe Mathieu-Daudé
2023-02-16 2:57 ` [PATCH v2 30/30] tcg/i386: Honor 64-bit atomicity in 32-bit mode Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230216025739.1211680-18-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).