From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v1 11/19] target/arm: Hoist finalize_memop out of do_fp_{ld, st}
Date: Wed, 15 Feb 2023 17:08:46 -1000 [thread overview]
Message-ID: <20230216030854.1212208-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230216030854.1212208-1-richard.henderson@linaro.org>
We are going to need the complete memop beforehand,
so let's not compute it twice.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 42 +++++++++++++++++---------------------
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fd499a208d..cc857d60d7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -955,16 +955,14 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
/*
* Store from FP register to memory
*/
-static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
+static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, MemOp mop)
{
/* This writes the bottom N bits of a 128 bit wide vector to memory */
TCGv_i64 tmplo = tcg_temp_new_i64();
- MemOp mop;
tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64));
- if (size < MO_128) {
- mop = finalize_memop(s, size);
+ if ((mop & MO_SIZE) < MO_128) {
tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
TCGv_i64 tmphi = tcg_temp_new_i64();
@@ -974,7 +972,6 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
tcg_gen_concat_i64_i128(t16, tmplo, tmphi);
tcg_temp_free_i64(tmphi);
- mop = finalize_memop(s, size);
tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop);
tcg_temp_free_i128(t16);
}
@@ -985,20 +982,17 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
/*
* Load from memory to FP register
*/
-static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
+static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, MemOp mop)
{
/* This always zero-extends and writes to a full 128 bit wide vector */
TCGv_i64 tmplo = tcg_temp_new_i64();
TCGv_i64 tmphi = NULL;
- MemOp mop;
- if (size < MO_128) {
- mop = finalize_memop(s, size);
+ if ((mop & MO_SIZE) < MO_128) {
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
TCGv_i128 t16 = tcg_temp_new_i128();
- mop = finalize_memop(s, size);
tcg_gen_qemu_ld_i128(t16, tcg_addr, get_mem_index(s), mop);
tmphi = tcg_temp_new_i64();
@@ -2910,6 +2904,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
bool is_signed = false;
int size = 2;
TCGv_i64 tcg_rt, clean_addr;
+ MemOp mop;
if (is_vector) {
if (opc == 3) {
@@ -2933,13 +2928,13 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
clean_addr = new_tmp_a64(s);
gen_pc_plus_diff(s, clean_addr, imm);
+
+ mop = finalize_memop(s, size + is_signed * MO_SIGN);
if (is_vector) {
- do_fp_ld(s, rt, clean_addr, size);
+ do_fp_ld(s, rt, clean_addr, mop);
} else {
/* Only unsigned 32bit loads target 32bit registers. */
bool iss_sf = opc != 0;
- MemOp memop = finalize_memop(s, size + is_signed * MO_SIGN);
-
do_gpr_ld(s, tcg_rt, clean_addr, mop, false, true, rt, iss_sf, false);
}
}
@@ -3076,16 +3071,17 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
(wback || rn != 31) && !set_tag, 2 << size);
if (is_vector) {
+ MemOp mop = finalize_memop(s, size);
if (is_load) {
- do_fp_ld(s, rt, clean_addr, size);
+ do_fp_ld(s, rt, clean_addr, mop);
} else {
- do_fp_st(s, rt, clean_addr, size);
+ do_fp_st(s, rt, clean_addr, mop);
}
tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
if (is_load) {
- do_fp_ld(s, rt2, clean_addr, size);
+ do_fp_ld(s, rt2, clean_addr, mop);
} else {
- do_fp_st(s, rt2, clean_addr, size);
+ do_fp_st(s, rt2, clean_addr, mop);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
@@ -3269,9 +3265,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
if (is_vector) {
if (is_store) {
- do_fp_st(s, rt, clean_addr, size);
+ do_fp_st(s, rt, clean_addr, memop);
} else {
- do_fp_ld(s, rt, clean_addr, size);
+ do_fp_ld(s, rt, clean_addr, memop);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
@@ -3377,9 +3373,9 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
if (is_vector) {
if (is_store) {
- do_fp_st(s, rt, clean_addr, size);
+ do_fp_st(s, rt, clean_addr, memop);
} else {
- do_fp_ld(s, rt, clean_addr, size);
+ do_fp_ld(s, rt, clean_addr, memop);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
@@ -3463,9 +3459,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
if (is_vector) {
if (is_store) {
- do_fp_st(s, rt, clean_addr, size);
+ do_fp_st(s, rt, clean_addr, memop);
} else {
- do_fp_ld(s, rt, clean_addr, size);
+ do_fp_ld(s, rt, clean_addr, memop);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
--
2.34.1
next prev parent reply other threads:[~2023-02-16 3:11 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 3:08 [PATCH v1 00/19] target/arm: Implement FEAT_LSE2 Richard Henderson
2023-02-16 3:08 ` [PATCH v1 01/19] target/arm: Make cpu_exclusive_high hold the high bits Richard Henderson
2023-02-23 15:14 ` Peter Maydell
2023-02-23 16:12 ` Richard Henderson
2023-02-23 16:51 ` Peter Maydell
2023-02-23 17:08 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 02/19] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Richard Henderson
2023-02-16 3:08 ` [PATCH v1 03/19] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} Richard Henderson
2023-02-23 15:23 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 04/19] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G Richard Henderson
2023-02-23 15:24 ` Peter Maydell
2023-02-23 16:20 ` Richard Henderson
2023-02-23 16:53 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 05/19] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r Richard Henderson
2023-02-23 15:36 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 06/19] target/arm: Sink gen_mte_check1 into load/store_exclusive Richard Henderson
2023-02-23 15:40 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 07/19] target/arm: Add feature test for FEAT_LSE2 Richard Henderson
2023-02-23 15:43 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 08/19] target/arm: Add atom_data to DisasContext Richard Henderson
2023-02-23 15:47 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 09/19] target/arm: Load/store integer pair with one tcg operation Richard Henderson
2023-02-23 15:57 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 10/19] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Richard Henderson
2023-02-23 16:03 ` Peter Maydell
2023-02-16 3:08 ` Richard Henderson [this message]
2023-02-23 16:04 ` [PATCH v1 11/19] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Peter Maydell
2023-02-16 3:08 ` [PATCH v1 12/19] target/arm: Pass memop to gen_mte_check1* Richard Henderson
2023-02-23 16:08 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 13/19] target/arm: Pass single_memop to gen_mte_checkN Richard Henderson
2023-02-23 16:10 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 14/19] target/arm: Check alignment in helper_mte_check Richard Henderson
2023-02-23 16:28 ` Peter Maydell
2023-02-23 16:38 ` Richard Henderson
2023-02-23 16:54 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 15/19] target/arm: Add SCTLR.nAA to TBFLAG_A64 Richard Henderson
2023-02-23 16:32 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 16/19] target/arm: Relax ordered/atomic alignment checks for LSE2 Richard Henderson
2023-02-23 16:49 ` Peter Maydell
2023-02-23 17:16 ` Richard Henderson
2023-02-23 17:22 ` Peter Maydell
2023-02-23 17:27 ` Richard Henderson
2023-02-16 3:08 ` [PATCH v1 17/19] target/arm: Move mte check for store-exclusive Richard Henderson
2023-02-23 16:36 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 18/19] test/tcg/multiarch: Adjust sigbus.c Richard Henderson
2023-02-23 16:36 ` Peter Maydell
2023-02-16 3:08 ` [PATCH v1 19/19] target/arm: Enable FEAT_LSE2 for -cpu max Richard Henderson
2023-02-23 16:37 ` Peter Maydell
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