From: Ivan Klokov <ivan.klokov@syntacore.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Alistair.Francis@wdc.com,
palmer@dabbelt.com, Ivan Klokov <ivan.klokov@syntacore.com>
Subject: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble
Date: Fri, 17 Feb 2023 19:10:27 +0300 [thread overview]
Message-ID: <20230217161027.56859-1-ivan.klokov@syntacore.com> (raw)
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
---
v2:
- added fixes line
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..54455aaaa8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_data opcode_data[] = {
{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
--
2.34.1
next reply other threads:[~2023-02-17 16:12 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 16:10 Ivan Klokov [this message]
2023-02-17 17:51 ` [PATCH] [PATCH] disas/riscv Fix ctzw disassemble Daniel Henrique Barboza
2023-02-18 12:40 ` weiwei
-- strict thread matches above, loose matches on Subject: below --
2023-02-17 15:14 Ivan Klokov
2023-02-17 15:45 ` Daniel Henrique Barboza
2023-03-02 0:32 ` Palmer Dabbelt
2023-03-02 7:42 ` Ivan Klokov
2023-03-05 20:46 ` Palmer Dabbelt
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