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From: Palmer Dabbelt <palmer@rivosinc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org,          qemu-devel@nongnu.org,
	Alistair Francis <alistair.francis@wdc.com>,
	LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Weiwei Li <liweiwei@iscas.ac.cn>,
	 ilippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
	Bin Meng <bmeng.cn@gmail.com>,
	 Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Frank Chang <frank.chang@sifive.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PULL 6/9] MAINTAINERS: Add some RISC-V reviewers
Date: Fri, 17 Feb 2023 09:52:00 -0800	[thread overview]
Message-ID: <20230217175203.19510-7-palmer@rivosinc.com> (raw)
In-Reply-To: <20230217175203.19510-1-palmer@rivosinc.com>

From: Alistair Francis <alistair.francis@wdc.com>

This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20230209003308.738237-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,6 +287,9 @@ RISC-V TCG CPUs
 M: Palmer Dabbelt <palmer@dabbelt.com>
 M: Alistair Francis <alistair.francis@wdc.com>
 M: Bin Meng <bin.meng@windriver.com>
+R: Weiwei Li <liweiwei@iscas.ac.cn>
+R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/
-- 
2.39.0



  parent reply	other threads:[~2023-02-17 17:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-17 17:51 [PULL 0/9] Fourth RISC-V PR for QEMU 8.0 Palmer Dabbelt
2023-02-17 17:51 ` [PULL 1/9] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Palmer Dabbelt
2023-02-17 17:51 ` [PULL 2/9] hw/riscv/boot.c: consolidate all kernel init " Palmer Dabbelt
2023-02-17 17:51 ` [PULL 3/9] hw/riscv/boot.c: make riscv_load_initrd() static Palmer Dabbelt
2023-02-17 17:51 ` [PULL 4/9] roms/opensbi: Upgrade from v1.1 to v1.2 Palmer Dabbelt
2023-02-17 17:51 ` [PULL 5/9] target/riscv: Remove privileged spec version restriction for RVV Palmer Dabbelt
2023-02-17 17:52 ` Palmer Dabbelt [this message]
2023-02-17 17:52 ` [PULL 7/9] target/riscv: Smepmp: Skip applying default rules when address matches Palmer Dabbelt
2023-02-17 17:52 ` [PULL 8/9] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Palmer Dabbelt
2023-02-17 17:52 ` [PULL 9/9] target/riscv: Fix vslide1up.vf and vslide1down.vf Palmer Dabbelt
2023-02-21 16:43 ` [PULL 0/9] Fourth RISC-V PR for QEMU 8.0 Peter Maydell
2023-02-22 15:56   ` Palmer Dabbelt
2023-02-23 22:49     ` Palmer Dabbelt
2023-02-24  6:56       ` Thomas Huth
2023-02-24 18:52         ` Peter Maydell
2023-02-24 19:01           ` Palmer Dabbelt

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