From: Fabiano Rosas <farosas@suse.de>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Claudio Fontana" <cfontana@suse.de>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Alexander Graf" <agraf@csgraf.de>,
"Cornelia Huck" <cohuck@redhat.com>
Subject: [PATCH v6 16/29] target/arm: Move cortex sysregs into cpu64.c
Date: Fri, 17 Feb 2023 17:11:37 -0300 [thread overview]
Message-ID: <20230217201150.22032-17-farosas@suse.de> (raw)
In-Reply-To: <20230217201150.22032-1-farosas@suse.de>
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into cpu64.c along with the cortex cpus
definition.
This code defines registers for 64-bit cpus but it is shared by the 32
bit "max" CPU, so use an ifdef instead of meson to keep the rest of
the file 64-bit only.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpregs.h | 6 ++++
target/arm/cpu64.c | 63 ++++++++++++++++++++++++++++++++++++++++++
target/arm/cpu_tcg.c | 59 ---------------------------------------
target/arm/internals.h | 6 ----
target/arm/meson.build | 2 +-
5 files changed, 70 insertions(+), 66 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1ee64e99de..b04d344a9f 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1071,4 +1071,10 @@ static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
ri->crn, ri->crm);
}
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..ab2818dc15 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -29,6 +29,68 @@
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
#include "internals.h"
+#include "cpregs.h"
+
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2CTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .readfn = l2ctlr_read,
+ .writefn = arm_cp_write_ignore },
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ECTLR",
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR",
+ .cp = 15, .opc1 = 0, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUECTLR",
+ .cp = 15, .opc1 = 1, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUMERRSR",
+ .cp = 15, .opc1 = 2, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "L2MERRSR",
+ .cp = 15, .opc1 = 3, .crm = 15,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
+#ifdef TARGET_AARCH64
static void aarch64_a35_initfn(Object *obj)
{
@@ -1425,3 +1487,4 @@ static void aarch64_cpu_register_types(void)
}
type_init(aarch64_cpu_register_types)
+#endif /* TARGET_AARCH64 */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ccde5080eb..64d5a785c1 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -90,65 +90,6 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_dfr0 = t;
}
-#ifndef CONFIG_USER_ONLY
-static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- ARMCPU *cpu = env_archcpu(env);
-
- /* Number of cores is in [25:24]; otherwise we RAZ */
- return (cpu->core_count - 1) << 24;
-}
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2CTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ECTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR",
- .cp = 15, .opc1 = 0, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUECTLR",
- .cp = 15, .opc1 = 1, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUMERRSR",
- .cp = 15, .opc1 = 2, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2MERRSR",
- .cp = 15, .opc1 = 3, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-};
-
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
-{
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
-}
-#endif /* !CONFIG_USER_ONLY */
-
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 6ebe59959e..72d58c706c 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1366,12 +1366,6 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
#endif
-#ifdef CONFIG_USER_ONLY
-static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-#else
-void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
-#endif
-
bool el_is_in_host(CPUARMState *env, int el);
void aa32_max_features(ARMCPU *cpu);
diff --git a/target/arm/meson.build b/target/arm/meson.build
index a5191b57e1..b0bc8a3cea 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
arm_ss = ss.source_set()
arm_ss.add(files(
'cpu.c',
+ 'cpu64.c',
'debug_helper.c',
'gdbstub.c',
'helper.c',
@@ -12,7 +13,6 @@ arm_ss.add(zlib)
arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
- 'cpu64.c',
'gdbstub64.c',
))
--
2.35.3
next prev parent reply other threads:[~2023-02-17 20:15 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 20:11 [PATCH v6 00/29] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 01/29] target/arm: rename handle_semihosting to tcg_handle_semihosting Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 02/29] target/arm: wrap psci call with tcg_enabled Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 03/29] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 04/29] target/arm: Move PC alignment check Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 05/29] target/arm: Move cpregs code out of cpu.h Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 06/29] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled Fabiano Rosas
2023-02-18 4:06 ` Richard Henderson
2023-02-17 20:11 ` [PATCH v6 07/29] target/arm: Wrap TCG-only code in debug_helper.c Fabiano Rosas
2023-02-18 4:10 ` Richard Henderson
2023-02-17 20:11 ` [PATCH v6 08/29] target/arm: move translate modules to tcg/ Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 09/29] target/arm: move helpers " Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 10/29] target/arm: Move psci.c into the tcg directory Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 11/29] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 12/29] target/arm: Move hflags code into the tcg directory Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 13/29] target/arm: Move regime_using_lpae_format into internal.h Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 14/29] target/arm: Don't access TCG code when debugging with KVM Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 15/29] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code Fabiano Rosas
2023-02-17 20:11 ` Fabiano Rosas [this message]
2023-02-18 4:26 ` [PATCH v6 16/29] target/arm: Move cortex sysregs into cpu64.c Richard Henderson
2023-02-17 20:11 ` [PATCH v6 17/29] tests/avocado: Skip tests that require a missing accelerator Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 18/29] tests/avocado: Tag TCG tests with accel:tcg Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 19/29] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
2023-02-21 14:16 ` Peter Maydell
2023-02-22 13:58 ` Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 20/29] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 21/29] target/arm: Use "max" as default cpu for the virt machine with KVM Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 22/29] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 23/29] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 24/29] target/avocado: Pass parameters to migration test Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 25/29] tests/avocado: add machine:none tag to version.py Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 26/29] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 27/29] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 28/29] gitlab-ci: Check building KVM-only aarch64 target Fabiano Rosas
2023-02-17 20:11 ` [PATCH v6 29/29] tests/qtest: Fix tests when no KVM or TCG are present Fabiano Rosas
2023-02-21 14:21 ` [PATCH v6 00/29] target/arm: Allow CONFIG_TCG=n builds Peter Maydell
2023-02-22 12:40 ` Fabiano Rosas
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