From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com,
eduardo@habkost.net, peter.maydell@linaro.org, mrolnik@gmail.com,
tsimpson@quicinc.com, gaosong@loongson.cn,
yangxiaojuan@loongson.cn, edgar.iglesias@gmail.com,
philmd@linaro.org, shorne@gmail.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
ysato@users.sourceforge.jp, mark.cave-ayland@ilande.co.uk,
atar4qemu@gmail.com, kbastian@mail.uni-paderborn.de
Subject: [PATCH v2 07/27] target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`
Date: Tue, 21 Feb 2023 23:17:58 +0100 [thread overview]
Message-ID: <20230221221818.9382-8-anjo@rev.ng> (raw)
In-Reply-To: <20230221221818.9382-1-anjo@rev.ng>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/helper.c | 2 +-
target/i386/tcg/tcg-cpu.c | 6 +++---
target/i386/tcg/translate.c | 26 +++++++++++++-------------
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 0ac2da066d..8857444819 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -520,7 +520,7 @@ static inline target_ulong get_memio_eip(CPUX86State *env)
}
/* Per x86_restore_state_to_opc. */
- if (TARGET_TB_PCREL) {
+ if (cs->tcg_cflags & CF_PCREL) {
return (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
return data[0] - env->segs[R_CS].base;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 79ac5908f7..c090ce152b 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -49,8 +49,8 @@ static void x86_cpu_exec_exit(CPUState *cs)
static void x86_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- /* The instruction pointer is always up to date with TARGET_TB_PCREL. */
- if (!TARGET_TB_PCREL) {
+ /* The instruction pointer is always up to date with CF_PCREL. */
+ if (!(tb_cflags(tb) & CF_PCREL)) {
CPUX86State *env = cs->env_ptr;
env->eip = tb_pc(tb) - tb->cs_base;
}
@@ -64,7 +64,7 @@ static void x86_restore_state_to_opc(CPUState *cs,
CPUX86State *env = &cpu->env;
int cc_op = data[1];
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(tb) & CF_PCREL) {
env->eip = (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
env->eip = data[0] - tb->cs_base;
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9d9392b009..3fed6d96f9 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -545,7 +545,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
static void gen_update_eip_cur(DisasContext *s)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, s->base.pc_next - s->pc_save);
} else {
tcg_gen_movi_tl(cpu_eip, s->base.pc_next - s->cs_base);
@@ -556,7 +556,7 @@ static void gen_update_eip_cur(DisasContext *s)
static void gen_update_eip_next(DisasContext *s)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save);
} else {
tcg_gen_movi_tl(cpu_eip, s->pc - s->cs_base);
@@ -588,7 +588,7 @@ static TCGv_i32 eip_next_i32(DisasContext *s)
if (CODE64(s)) {
return tcg_constant_i32(-1);
}
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(ret, cpu_eip);
tcg_gen_addi_i32(ret, ret, s->pc - s->pc_save);
@@ -601,7 +601,7 @@ static TCGv_i32 eip_next_i32(DisasContext *s)
static TCGv eip_next_tl(DisasContext *s)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv ret = tcg_temp_new();
tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save);
return ret;
@@ -613,7 +613,7 @@ static TCGv eip_next_tl(DisasContext *s)
static TCGv eip_cur_tl(DisasContext *s)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv ret = tcg_temp_new();
tcg_gen_addi_tl(ret, cpu_eip, s->base.pc_next - s->pc_save);
return ret;
@@ -1830,7 +1830,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- /* The CC_OP value is no longer predictable. */
+ /* The CC_OP value is no longer predictable. */
set_cc_op(s, CC_OP_DYNAMIC);
}
@@ -1923,7 +1923,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
gen_op_ld_v(s, ot, s->T0, s->A0);
else
gen_op_mov_v_reg(s, ot, s->T0, op1);
-
+
if (is_right) {
switch (ot) {
case MO_8:
@@ -2319,7 +2319,7 @@ static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a, bool is_vsib)
ea = cpu_regs[a.base];
}
if (!ea) {
- if (TARGET_TB_PCREL && a.base == -2) {
+ if (tb_cflags(s->base.tb) & CF_PCREL && a.base == -2) {
/* With cpu_eip ~= pc_save, the expression is pc-relative. */
tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save);
} else {
@@ -2867,7 +2867,7 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
if (!CODE64(s)) {
if (ot == MO_16) {
mask = 0xffff;
- if (TARGET_TB_PCREL && CODE32(s)) {
+ if (tb_cflags(s->base.tb) & CF_PCREL && CODE32(s)) {
use_goto_tb = false;
}
} else {
@@ -2879,7 +2879,7 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
gen_update_cc_op(s);
set_cc_op(s, CC_OP_DYNAMIC);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, new_pc - s->pc_save);
/*
* If we can prove the branch does not leave the page and we have
@@ -2896,13 +2896,13 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
translator_use_goto_tb(&s->base, new_eip + s->cs_base)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
- if (!TARGET_TB_PCREL) {
+ if (!(tb_cflags(s->base.tb) & CF_PCREL)) {
tcg_gen_movi_tl(cpu_eip, new_eip);
}
tcg_gen_exit_tb(s->base.tb, tb_num);
s->base.is_jmp = DISAS_NORETURN;
} else {
- if (!TARGET_TB_PCREL) {
+ if (!(tb_cflags(s->base.tb) & CF_PCREL)) {
tcg_gen_movi_tl(cpu_eip, new_eip);
}
if (s->jmp_opt) {
@@ -7065,7 +7065,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
target_ulong pc_arg = dc->base.pc_next;
dc->prev_insn_end = tcg_last_op();
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg -= dc->cs_base;
pc_arg &= ~TARGET_PAGE_MASK;
}
--
2.39.1
next prev parent reply other threads:[~2023-02-21 22:24 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-21 22:17 [PATCH v2 00/27] Replace TARGET_TB_PCREL with CF_PCREL Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 01/27] include/exec: Introduce `CF_PCREL` Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 02/27] target/i386: set `CF_PCREL` in `x86_cpu_realizefn` Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 03/27] target/arm: set `CF_PCREL` in `arm_cpu_realizefn` Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 04/27] accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL` Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 05/27] include/exec: " Anton Johansson via
2023-02-21 22:17 ` [PATCH v2 06/27] target/arm: " Anton Johansson via
2023-02-21 22:17 ` Anton Johansson via [this message]
2023-02-21 22:17 ` [PATCH v2 08/27] include/exec: Remove `TARGET_TB_PCREL` define Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 09/27] target/arm: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 10/27] target/i386: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 11/27] accel/tcg: Move jmp-cache `CF_PCREL` checks to caller Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 12/27] accel/tcg: Replace `tb_pc()` with `tb->pc` Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 13/27] target/tricore: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 14/27] target/sparc: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 15/27] target/sh4: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 16/27] target/rx: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 17/27] target/riscv: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 18/27] target/openrisc: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 19/27] target/mips: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 20/27] target/microblaze: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 21/27] target/loongarch: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 22/27] target/i386: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 23/27] target/hppa: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 24/27] target/hexagon: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 25/27] target/avr: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 26/27] target/arm: " Anton Johansson via
2023-02-21 22:18 ` [PATCH v2 27/27] include/exec: Remove `tb_pc()` Anton Johansson via
2023-02-21 22:39 ` [PATCH v2 00/27] Replace TARGET_TB_PCREL with CF_PCREL Philippe Mathieu-Daudé
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