From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH NOTFORMERGE v3 24/25] target/arm: Enable RME for -cpu max
Date: Tue, 21 Feb 2023 16:33:35 -1000 [thread overview]
Message-ID: <20230222023336.915045-25-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org>
Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing
various possible configurations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu64.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..70c173ee3d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -672,6 +672,40 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
cpu->isar.id_aa64mmfr0 = t;
}
+static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t value;
+
+ if (!visit_type_uint32(v, name, &value, errp)) {
+ return;
+ }
+
+ /* Encode the value for the GPCCR_EL3 field. */
+ switch (value) {
+ case 30:
+ case 34:
+ case 36:
+ case 39:
+ cpu->reset_l0gptsz = value - 30;
+ break;
+ default:
+ error_setg(errp, "invalid value for l0gptsz");
+ error_append_hint(errp, "valid values are 30, 34, 36, 39\n");
+ break;
+ }
+}
+
+static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t value = cpu->reset_l0gptsz + 30;
+
+ visit_type_uint32(v, name, &value, errp);
+}
+
static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1200,6 +1234,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP64(t, ID_AA64PFR0, RME, 1); /* FEAT_RME */
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
cpu->isar.id_aa64pfr0 = t;
@@ -1301,6 +1336,8 @@ static void aarch64_max_initfn(Object *obj)
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
cpu_max_set_sve_max_vq, NULL, NULL);
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
+ object_property_add(obj, "l0gptsz", "uint32", cpu_max_get_l0gptsz,
+ cpu_max_set_l0gptsz, NULL, NULL);
}
static const ARMCPUInfo aarch64_cpus[] = {
--
2.34.1
next prev parent reply other threads:[~2023-02-22 2:38 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-22 2:33 [PATCH v3 00/25] target/arm: Implement FEAT_RME Richard Henderson
2023-02-22 2:33 ` [PATCH v3 01/25] target/arm: Handle m-profile in arm_is_secure Richard Henderson
2023-02-24 13:14 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 02/25] target/arm: Stub arm_hcr_el2_eff for m-profile Richard Henderson
2023-02-24 13:15 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 03/25] target/arm: Diagnose incorrect usage of arm_is_secure subroutines Richard Henderson
2023-02-22 9:39 ` Philippe Mathieu-Daudé
2023-02-24 13:16 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 04/25] target/arm: Rewrite check_s2_mmu_setup Richard Henderson
2023-02-24 13:53 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme Richard Henderson
2023-02-22 9:41 ` Philippe Mathieu-Daudé
2023-02-22 2:33 ` [PATCH v3 06/25] target/arm: Update SCR and HCR for RME Richard Henderson
2023-02-22 2:33 ` [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1 Richard Henderson
2023-02-24 14:24 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 08/25] target/arm: Add RME cpregs Richard Henderson
2023-02-22 2:33 ` [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace Richard Henderson
2023-02-22 2:33 ` [PATCH v3 10/25] include/exec/memattrs: Add two bits of space to MemTxAttrs Richard Henderson
2023-02-22 2:33 ` [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Richard Henderson
2023-02-22 2:33 ` [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Richard Henderson
2023-02-22 9:44 ` Philippe Mathieu-Daudé
2023-02-22 2:33 ` [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c Richard Henderson
2023-02-22 9:44 ` Philippe Mathieu-Daudé
2023-02-24 13:18 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c Richard Henderson
2023-02-22 2:33 ` [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime Richard Henderson
2023-02-24 14:28 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 16/25] target/arm: Handle Block and Page bits for security space Richard Henderson
2023-02-24 14:51 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 17/25] target/arm: Handle no-execute for Realm and Root regimes Richard Henderson
2023-02-24 14:58 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 18/25] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Richard Henderson
2023-02-22 2:33 ` [PATCH v3 19/25] target/arm: Move s1_is_el0 into S1Translate Richard Henderson
2023-02-22 9:46 ` Philippe Mathieu-Daudé
2023-02-22 2:33 ` [PATCH v3 20/25] target/arm: Use get_phys_addr_with_struct for stage2 Richard Henderson
2023-02-22 9:50 ` Philippe Mathieu-Daudé
2023-02-24 15:06 ` Peter Maydell
2023-02-22 2:33 ` [PATCH v3 21/25] target/arm: Add GPC syndrome Richard Henderson
2023-02-22 2:33 ` [PATCH v3 22/25] target/arm: Implement GPC exceptions Richard Henderson
2023-02-22 2:33 ` [PATCH v3 23/25] target/arm: Implement the granule protection check Richard Henderson
2023-02-22 2:33 ` Richard Henderson [this message]
2023-02-22 2:33 ` [PATCH NOTFORMERGE v3 25/25] hw/arm/virt: Add some memory for Realm Management Monitor Richard Henderson
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