* [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:40 ` Daniel Henrique Barboza
2023-02-24 4:08 ` [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/csr.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fa17d7770c..feae23cab0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
if (riscv_cpu_mxl(env) == MXL_RV64) {
- mask |= MENVCFG_PBMTE | MENVCFG_STCE;
+ mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cfg->ext_sstc ? MENVCFG_STCE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+ RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+ uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cfg->ext_sstc ? MENVCFG_STCE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
2023-02-24 4:08 ` [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Weiwei Li
@ 2023-02-24 11:40 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:40 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/csr.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fa17d7770c..feae23cab0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - mask |= MENVCFG_PBMTE | MENVCFG_STCE;
> + mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
> + (cfg->ext_sstc ? MENVCFG_STCE : 0);
> }
> env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
>
> @@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
> static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
> + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> + uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
> + (cfg->ext_sstc ? MENVCFG_STCE : 0);
> uint64_t valh = (uint64_t)val << 32;
>
> env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
2023-02-24 4:08 ` [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:44 ` Daniel Henrique Barboza
2023-02-24 12:19 ` Andrew Jones
2023-02-24 4:08 ` [PATCH 3/6] target/riscv: Add csr support for svadu Weiwei Li
` (4 subsequent siblings)
6 siblings, 2 replies; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/csr.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index feae23cab0..02cb2c2bb7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
return ret;
}
- *val = env->henvcfg;
+ /*
+ * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
+ * henvcfg.stce is read_only 0 when menvcfg.stce = 0
+ */
+ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
- mask |= HENVCFG_PBMTE | HENVCFG_STCE;
+ mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
return ret;
}
- *val = env->henvcfg >> 32;
+ *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
+ env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
+ uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
2023-02-24 4:08 ` [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li
@ 2023-02-24 11:44 ` Daniel Henrique Barboza
2023-02-24 12:19 ` Andrew Jones
1 sibling, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:44 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/csr.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index feae23cab0..02cb2c2bb7 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> return ret;
> }
>
> - *val = env->henvcfg;
> + /*
> + * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
> + * henvcfg.stce is read_only 0 when menvcfg.stce = 0
> + */
> + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
> return RISCV_EXCP_NONE;
> }
>
> @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> }
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - mask |= HENVCFG_PBMTE | HENVCFG_STCE;
> + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> }
>
> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
> @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> return ret;
> }
>
> - *val = env->henvcfg >> 32;
> + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
> + env->menvcfg)) >> 32;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
> + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> uint64_t valh = (uint64_t)val << 32;
> RISCVException ret;
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
2023-02-24 4:08 ` [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li
2023-02-24 11:44 ` Daniel Henrique Barboza
@ 2023-02-24 12:19 ` Andrew Jones
2023-02-24 12:36 ` liweiwei
1 sibling, 1 reply; 17+ messages in thread
From: Andrew Jones @ 2023-02-24 12:19 UTC (permalink / raw)
To: Weiwei Li
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/csr.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index feae23cab0..02cb2c2bb7 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> return ret;
> }
>
> - *val = env->henvcfg;
> + /*
> + * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
> + * henvcfg.stce is read_only 0 when menvcfg.stce = 0
> + */
> + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
> return RISCV_EXCP_NONE;
> }
>
> @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> }
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - mask |= HENVCFG_PBMTE | HENVCFG_STCE;
> + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
nit:
While HENVCFG_PBMTE == MENVCFG_PBMTE, I'd prefer we use
MENVCFG_* with menvcfg and HENVCFG_* with henvcfg.
> }
>
> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
> @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> return ret;
> }
>
> - *val = env->henvcfg >> 32;
> + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
> + env->menvcfg)) >> 32;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
> + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> uint64_t valh = (uint64_t)val << 32;
> RISCVException ret;
>
> --
> 2.25.1
>
>
Thanks,
drew
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
2023-02-24 12:19 ` Andrew Jones
@ 2023-02-24 12:36 ` liweiwei
2023-03-02 1:36 ` Palmer Dabbelt
0 siblings, 1 reply; 17+ messages in thread
From: liweiwei @ 2023-02-24 12:36 UTC (permalink / raw)
To: Andrew Jones
Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On 2023/2/24 20:19, Andrew Jones wrote:
> On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
>> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> target/riscv/csr.c | 13 +++++++++----
>> 1 file changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index feae23cab0..02cb2c2bb7 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
>> return ret;
>> }
>>
>> - *val = env->henvcfg;
>> + /*
>> + * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
>> + * henvcfg.stce is read_only 0 when menvcfg.stce = 0
>> + */
>> + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
>> return RISCV_EXCP_NONE;
>> }
>>
>> @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
>> }
>>
>> if (riscv_cpu_mxl(env) == MXL_RV64) {
>> - mask |= HENVCFG_PBMTE | HENVCFG_STCE;
>> + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> nit:
>
> While HENVCFG_PBMTE == MENVCFG_PBMTE, I'd prefer we use
> MENVCFG_* with menvcfg and HENVCFG_* with henvcfg.
Yeah. I agree. However, I think this mask is finally used for henvcfg.
We just use menvcfg to mask the bits
when the same bits are zero. So I didn't modify HENVCFG_* here.
Regards,
Weiwei Li
>
>> }
>>
>> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
>> @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
>> return ret;
>> }
>>
>> - *val = env->henvcfg >> 32;
>> + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
>> + env->menvcfg)) >> 32;
>> return RISCV_EXCP_NONE;
>> }
>>
>> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
>> target_ulong val)
>> {
>> - uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
>> + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
>> uint64_t valh = (uint64_t)val << 32;
>> RISCVException ret;
>>
>> --
>> 2.25.1
>>
>>
> Thanks,
> drew
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
2023-02-24 12:36 ` liweiwei
@ 2023-03-02 1:36 ` Palmer Dabbelt
0 siblings, 0 replies; 17+ messages in thread
From: Palmer Dabbelt @ 2023-03-02 1:36 UTC (permalink / raw)
To: liweiwei
Cc: ajones, qemu-riscv, qemu-devel, Alistair Francis, bin.meng,
dbarboza, zhiwei_liu, wangjunqiang, lazyparser
On Fri, 24 Feb 2023 04:36:43 PST (-0800), liweiwei@iscas.ac.cn wrote:
>
> On 2023/2/24 20:19, Andrew Jones wrote:
>> On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
>>> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>>>
>>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>>> ---
>>> target/riscv/csr.c | 13 +++++++++----
>>> 1 file changed, 9 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>> index feae23cab0..02cb2c2bb7 100644
>>> --- a/target/riscv/csr.c
>>> +++ b/target/riscv/csr.c
>>> @@ -1956,7 +1956,11 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
>>> return ret;
>>> }
>>>
>>> - *val = env->henvcfg;
>>> + /*
>>> + * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
>>> + * henvcfg.stce is read_only 0 when menvcfg.stce = 0
>>> + */
>>> + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
>>> return RISCV_EXCP_NONE;
>>> }
>>>
>>> @@ -1972,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
>>> }
>>>
>>> if (riscv_cpu_mxl(env) == MXL_RV64) {
>>> - mask |= HENVCFG_PBMTE | HENVCFG_STCE;
>>> + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
>> nit:
>>
>> While HENVCFG_PBMTE == MENVCFG_PBMTE, I'd prefer we use
>> MENVCFG_* with menvcfg and HENVCFG_* with henvcfg.
>
> Yeah. I agree. However, I think this mask is finally used for henvcfg.
> We just use menvcfg to mask the bits
>
> when the same bits are zero. So I didn't modify HENVCFG_* here.
I guess it's kind of bikeshedding because the bits are the same, but
what's in the patch seems cleaner to me: we're writing the H state
masked by the M state, so we should use the H definitions (even if it
doesn't matter).
>
> Regards,
>
> Weiwei Li
>
>>
>>> }
>>>
>>> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
>>> @@ -1990,14 +1994,15 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
>>> return ret;
>>> }
>>>
>>> - *val = env->henvcfg >> 32;
>>> + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
>>> + env->menvcfg)) >> 32;
>>> return RISCV_EXCP_NONE;
>>> }
>>>
>>> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
>>> target_ulong val)
>>> {
>>> - uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
>>> + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
>>> uint64_t valh = (uint64_t)val << 32;
>>> RISCVException ret;
>>>
>>> --
>>> 2.25.1
>>>
>>>
>> Thanks,
>> drew
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] target/riscv: Add csr support for svadu
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
2023-02-24 4:08 ` [PATCH 1/6] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Weiwei Li
2023-02-24 4:08 ` [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:47 ` Daniel Henrique Barboza
2023-02-24 4:08 ` [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation Weiwei Li
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 4 ++++
target/riscv/csr.c | 17 +++++++++++------
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..bd272c35d1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -450,6 +450,7 @@ struct RISCVCPUConfig {
bool ext_zihintpause;
bool ext_smstateen;
bool ext_sstc;
+ bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8b0d7e20ea..fca7ef0cef 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -747,10 +747,12 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_HADE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
/* For RV32 */
+#define MENVCFGH_HADE BIT(29)
#define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31)
@@ -763,10 +765,12 @@ typedef enum RISCVException {
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_HADE MENVCFG_HADE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
/* For RV32 */
+#define HENVCFGH_HADE MENVCFGH_HADE
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 02cb2c2bb7..63e140e8ad 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cfg->ext_sstc ? MENVCFG_STCE : 0);
+ (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+ (cfg->ext_svadu ? MENVCFG_HADE : 0);
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
{
RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
- (cfg->ext_sstc ? MENVCFG_STCE : 0);
+ (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+ (cfg->ext_svadu ? MENVCFG_HADE : 0);
uint64_t valh = (uint64_t)val << 32;
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
/*
* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
* henvcfg.stce is read_only 0 when menvcfg.stce = 0
+ * henvcfg.hade is read_only 0 when menvcfg.hade = 0
*/
- *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
+ *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
+ env->menvcfg);
return RISCV_EXCP_NONE;
}
@@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
}
if (riscv_cpu_mxl(env) == MXL_RV64) {
- mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+ mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
return ret;
}
- *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
+ *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
env->menvcfg)) >> 32;
return RISCV_EXCP_NONE;
}
@@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val)
{
- uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
+ uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
+ HENVCFG_HADE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] target/riscv: Add csr support for svadu
2023-02-24 4:08 ` [PATCH 3/6] target/riscv: Add csr support for svadu Weiwei Li
@ 2023-02-24 11:47 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:47 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> Add ext_svadu property
> Add HADE field in *envcfg:
> * menvcfg.HADE is read-only zero if Svadu is not implemented.
> * henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/csr.c | 17 +++++++++++------
> 3 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7128438d8e..bd272c35d1 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -450,6 +450,7 @@ struct RISCVCPUConfig {
> bool ext_zihintpause;
> bool ext_smstateen;
> bool ext_sstc;
> + bool ext_svadu;
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 8b0d7e20ea..fca7ef0cef 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -747,10 +747,12 @@ typedef enum RISCVException {
> #define MENVCFG_CBIE (3UL << 4)
> #define MENVCFG_CBCFE BIT(6)
> #define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_HADE (1ULL << 61)
> #define MENVCFG_PBMTE (1ULL << 62)
> #define MENVCFG_STCE (1ULL << 63)
>
> /* For RV32 */
> +#define MENVCFGH_HADE BIT(29)
> #define MENVCFGH_PBMTE BIT(30)
> #define MENVCFGH_STCE BIT(31)
>
> @@ -763,10 +765,12 @@ typedef enum RISCVException {
> #define HENVCFG_CBIE MENVCFG_CBIE
> #define HENVCFG_CBCFE MENVCFG_CBCFE
> #define HENVCFG_CBZE MENVCFG_CBZE
> +#define HENVCFG_HADE MENVCFG_HADE
> #define HENVCFG_PBMTE MENVCFG_PBMTE
> #define HENVCFG_STCE MENVCFG_STCE
>
> /* For RV32 */
> +#define HENVCFGH_HADE MENVCFGH_HADE
> #define HENVCFGH_PBMTE MENVCFGH_PBMTE
> #define HENVCFGH_STCE MENVCFGH_STCE
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 02cb2c2bb7..63e140e8ad 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1890,7 +1890,8 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
> - (cfg->ext_sstc ? MENVCFG_STCE : 0);
> + (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> + (cfg->ext_svadu ? MENVCFG_HADE : 0);
> }
> env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
>
> @@ -1909,7 +1910,8 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> {
> RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
> uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
> - (cfg->ext_sstc ? MENVCFG_STCE : 0);
> + (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> + (cfg->ext_svadu ? MENVCFG_HADE : 0);
> uint64_t valh = (uint64_t)val << 32;
>
> env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
> @@ -1959,8 +1961,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> /*
> * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
> * henvcfg.stce is read_only 0 when menvcfg.stce = 0
> + * henvcfg.hade is read_only 0 when menvcfg.hade = 0
> */
> - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) | env->menvcfg);
> + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
> + env->menvcfg);
> return RISCV_EXCP_NONE;
> }
>
> @@ -1976,7 +1980,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
> }
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
> }
>
> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
> @@ -1994,7 +1998,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> return ret;
> }
>
> - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE) |
> + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
> env->menvcfg)) >> 32;
> return RISCV_EXCP_NONE;
> }
> @@ -2002,7 +2006,8 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
> static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE);
> + uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
> + HENVCFG_HADE);
> uint64_t valh = (uint64_t)val << 32;
> RISCVException ret;
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
` (2 preceding siblings ...)
2023-02-24 4:08 ` [PATCH 3/6] target/riscv: Add csr support for svadu Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:52 ` Daniel Henrique Barboza
2023-02-24 4:08 ` [PATCH 5/6] target/riscv: Add *envcfg.HADE " Weiwei Li
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.
henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.
Set *envcfg.PBMTE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 3 +++
target/riscv/cpu_helper.c | 10 ++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..2d99679f2f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -613,6 +613,9 @@ static void riscv_cpu_reset_hold(Object *obj)
env->bins = 0;
env->two_stage_lookup = false;
+ env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
+ env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
+
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
iprio = riscv_cpu_default_priority(i);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ad8d82662c..552c0f0b58 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -936,9 +936,15 @@ restart:
return TRANSLATE_FAIL;
}
+ bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+
+ if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
+ pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+ }
+
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
- } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
+ } else if (pbmte || cpu->cfg.ext_svnapot) {
ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
} else {
ppn = pte >> PTE_PPN_SHIFT;
@@ -950,7 +956,7 @@ restart:
if (!(pte & PTE_V)) {
/* Invalid PTE */
return TRANSLATE_FAIL;
- } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
+ } else if (!pbmte && (pte & PTE_PBMT)) {
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation
2023-02-24 4:08 ` [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation Weiwei Li
@ 2023-02-24 11:52 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:52 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> menvcfg.PBMTE bit controls whether the Svpbmt extension is available
> for use in S-mode and G-stage address translation.
>
> henvcfg.PBMTE bit controls whether the Svpbmt extension is available
> for use in VS-stage address translation.
>
> Set *envcfg.PBMTE default true for backward compatibility.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 3 +++
> target/riscv/cpu_helper.c | 10 ++++++++--
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dd2f0c753..2d99679f2f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -613,6 +613,9 @@ static void riscv_cpu_reset_hold(Object *obj)
> env->bins = 0;
> env->two_stage_lookup = false;
>
> + env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
> + env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
> +
> /* Initialized default priorities of local interrupts. */
> for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> iprio = riscv_cpu_default_priority(i);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index ad8d82662c..552c0f0b58 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -936,9 +936,15 @@ restart:
> return TRANSLATE_FAIL;
> }
>
> + bool pbmte = env->menvcfg & MENVCFG_PBMTE;
> +
> + if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
> + pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> + }
> +
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> ppn = pte >> PTE_PPN_SHIFT;
> - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
> + } else if (pbmte || cpu->cfg.ext_svnapot) {
> ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> } else {
> ppn = pte >> PTE_PPN_SHIFT;
> @@ -950,7 +956,7 @@ restart:
> if (!(pte & PTE_V)) {
> /* Invalid PTE */
> return TRANSLATE_FAIL;
> - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
> + } else if (!pbmte && (pte & PTE_PBMT)) {
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] target/riscv: Add *envcfg.HADE related check in address translation
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
` (3 preceding siblings ...)
2023-02-24 4:08 ` [PATCH 4/6] target/riscv: Add *envcfg.PBMTE related check in address translation Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:53 ` Daniel Henrique Barboza
2023-02-24 4:08 ` [PATCH 6/6] target/riscv: Export Svadu property Weiwei Li
2023-03-02 1:36 ` [PATCH 0/6] target/riscv: Add support for Svadu extension Palmer Dabbelt
6 siblings, 1 reply; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 6 ++++--
target/riscv/cpu_helper.c | 6 ++++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2d99679f2f..b81ab65de5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj)
env->bins = 0;
env->two_stage_lookup = false;
- env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
- env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
+ env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
+ env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
+ (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
/* Initialized default priorities of local interrupts. */
for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 552c0f0b58..9e122ee92a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,9 +937,11 @@ restart:
}
bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+ bool hade = env->menvcfg & MENVCFG_HADE;
if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+ hade = hade && (env->henvcfg & HENVCFG_HADE);
}
if (riscv_cpu_sxl(env) == MXL_RV32) {
@@ -998,6 +1000,10 @@ restart:
/* Page table updates need to be atomic with MTTCG enabled */
if (updated_pte != pte) {
+ if (!hade) {
+ return TRANSLATE_FAIL;
+ }
+
/*
* - if accessed or dirty bits need updating, and the PTE is
* in RAM, then we do so atomically with a compare and swap.
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] target/riscv: Add *envcfg.HADE related check in address translation
2023-02-24 4:08 ` [PATCH 5/6] target/riscv: Add *envcfg.HADE " Weiwei Li
@ 2023-02-24 11:53 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:53 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
> during single-stage address translation. When the hypervisor extension is
> implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
> enabled during G-stage address translation.
>
> Set *envcfg.HADE default true for backward compatibility.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 6 ++++--
> target/riscv/cpu_helper.c | 6 ++++++
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2d99679f2f..b81ab65de5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -613,8 +613,10 @@ static void riscv_cpu_reset_hold(Object *obj)
> env->bins = 0;
> env->two_stage_lookup = false;
>
> - env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0);
> - env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0);
> + env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
> + (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
> + env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
> + (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
>
> /* Initialized default priorities of local interrupts. */
> for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 552c0f0b58..9e122ee92a 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -937,9 +937,11 @@ restart:
> }
>
> bool pbmte = env->menvcfg & MENVCFG_PBMTE;
> + bool hade = env->menvcfg & MENVCFG_HADE;
>
> if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
> pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> + hade = hade && (env->henvcfg & HENVCFG_HADE);
> }
>
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> @@ -998,6 +1000,10 @@ restart:
>
> /* Page table updates need to be atomic with MTTCG enabled */
> if (updated_pte != pte) {
> + if (!hade) {
> + return TRANSLATE_FAIL;
> + }
> +
> /*
> * - if accessed or dirty bits need updating, and the PTE is
> * in RAM, then we do so atomically with a compare and swap.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] target/riscv: Export Svadu property
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
` (4 preceding siblings ...)
2023-02-24 4:08 ` [PATCH 5/6] target/riscv: Add *envcfg.HADE " Weiwei Li
@ 2023-02-24 4:08 ` Weiwei Li
2023-02-24 11:56 ` Daniel Henrique Barboza
2023-03-02 1:36 ` [PATCH 0/6] target/riscv: Add support for Svadu extension Palmer Dabbelt
6 siblings, 1 reply; 17+ messages in thread
From: Weiwei Li @ 2023-02-24 4:08 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Set it default true for backward compatibility
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b81ab65de5..d7c4c747dc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -107,6 +107,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
+ ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
@@ -1104,6 +1105,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] target/riscv: Export Svadu property
2023-02-24 4:08 ` [PATCH 6/6] target/riscv: Export Svadu property Weiwei Li
@ 2023-02-24 11:56 ` Daniel Henrique Barboza
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Henrique Barboza @ 2023-02-24 11:56 UTC (permalink / raw)
To: Weiwei Li, qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang,
lazyparser
On 2/24/23 01:08, Weiwei Li wrote:
> Set it default true for backward compatibility
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b81ab65de5..d7c4c747dc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -107,6 +107,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
> ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
> ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
> + ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
> ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
> @@ -1104,6 +1105,8 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
> +
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] target/riscv: Add support for Svadu extension
2023-02-24 4:08 [PATCH 0/6] target/riscv: Add support for Svadu extension Weiwei Li
` (5 preceding siblings ...)
2023-02-24 4:08 ` [PATCH 6/6] target/riscv: Export Svadu property Weiwei Li
@ 2023-03-02 1:36 ` Palmer Dabbelt
6 siblings, 0 replies; 17+ messages in thread
From: Palmer Dabbelt @ 2023-03-02 1:36 UTC (permalink / raw)
To: liweiwei
Cc: qemu-riscv, qemu-devel, Alistair Francis, bin.meng, dbarboza,
zhiwei_liu, wangjunqiang, lazyparser, liweiwei
On Thu, 23 Feb 2023 20:08:46 PST (-0800), liweiwei@iscas.ac.cn wrote:
> This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions.
>
> Specification for Svadu extension can be found in:
>
> https://github.com/riscv/riscv-svadu
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-svadu-upstream
>
> Weiwei Li (6):
> target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and
> Svpbmt/Sstc extensions
> target/riscv: Fix the relationship of PBMTE/STCE fields between
> menvcfg and henvcfg
> target/riscv: Add csr support for svadu
> target/riscv: Add *envcfg.PBMTE related check in address translation
> target/riscv: Add *envcfg.HADE related check in address translation
> target/riscv: Export Svadu property
>
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/cpu_helper.c | 16 ++++++++++++++--
> target/riscv/csr.c | 26 ++++++++++++++++++++------
> 5 files changed, 47 insertions(+), 8 deletions(-)
Thanks, this is queued up on riscv-to-apply.next .
^ permalink raw reply [flat|nested] 17+ messages in thread