qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Igor Mammedov <imammedo@redhat.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Kumar Patra <atishp@rivosinc.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH V4 6/8] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
Date: Fri, 24 Feb 2023 13:55:45 +0100	[thread overview]
Message-ID: <20230224135545.0df4222f@imammedo.users.ipa.redhat.com> (raw)
In-Reply-To: <20230224083701.2657063-7-sunilvl@ventanamicro.com>

On Fri, 24 Feb 2023 14:06:59 +0530
Sunil V L <sunilvl@ventanamicro.com> wrote:

> RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
> Table (RHCT). Add this to the ACPI tables.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  hw/riscv/virt-acpi-build.c | 76 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
> 
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 8b85b34c55..7037fe7634 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -33,6 +33,7 @@
>  #include "migration/vmstate.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/riscv_aclint.h"
>  
>  #define ACPI_BUILD_TABLE_SIZE             0x20000
>  
> @@ -83,6 +84,78 @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
>      aml_append(scope, dev);
>  }
>  
> +#define RHCT_NODE_ARRAY_OFFSET 56

same as previous patch, here should be proper comment
otherwise reviewer has no clue where to look for reference.

> +static void build_rhct(GArray *table_data,
> +                       BIOSLinker *linker,
> +                       RISCVVirtState *s)
> +{
> +    MachineState *ms = MACHINE(s);
> +    uint32_t acpi_proc_id = 0;
> +    int i, socket;
> +    RISCVCPU *cpu;
> +    char *isa;
> +    size_t len, aligned_len;
> +    uint32_t isa_offset, num_rhct_nodes;
> +
> +    AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> +                        .oem_table_id = s->oem_table_id };
> +
> +    acpi_table_begin(&table, table_data);
> +
> +    build_append_int_noprefix(table_data, 0x0, 4);   /* Reserved */
> +
> +    /* Time Base Frequency */
> +    build_append_int_noprefix(table_data,
> +                              RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);
> +
> +    /* ISA + N hart info */
> +    num_rhct_nodes = 1 + ms->smp.cpus;
> +
> +    /* Number of RHCT nodes*/
> +    build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> +
> +    /* Offset to the RHCT node array */
> +    build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);
> +
> +    /* ISA string node */
> +    isa_offset = table_data->len - table.table_offset;
> +    build_append_int_noprefix(table_data, 0, 2);   /* Type 0 */
> +
> +    cpu = &s->soc[0].harts[0];
> +    isa = riscv_isa_string(cpu);
> +    len = 8 + strlen(isa) + 1;
> +    aligned_len = (len % 2) ? (len + 1) : len;
> +
> +    build_append_int_noprefix(table_data, aligned_len, 2);   /* Length */
> +    build_append_int_noprefix(table_data, 0x1, 2);           /* Revision */
> +
> +    /* ISA string length including NUL */
> +    build_append_int_noprefix(table_data, strlen(isa) + 1, 2);
> +    g_array_append_vals(table_data, isa, strlen(isa) + 1);   /* ISA string */
> +
> +    if (aligned_len != len) {
> +        build_append_int_noprefix(table_data, 0x0, 1);   /* Optional Padding */
> +    }
> +
> +    for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> +        for (i = 0; i < s->soc[socket].num_harts; i++) {
> +            build_append_int_noprefix(table_data, 0xFFFF, 2);  /* Type */
> +            build_append_int_noprefix(table_data, 16, 2);      /* Length */
> +            build_append_int_noprefix(table_data, 0x1, 2);     /* Revision */
> +            build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */
> +
> +            /* ACPI Processor UID */
> +            build_append_int_noprefix(table_data, acpi_proc_id, 4);
> +
> +            /* Offsets[0] */
> +            build_append_int_noprefix(table_data, isa_offset, 4);
> +            acpi_proc_id++;
> +        }
> +    }
> +
> +    acpi_table_end(linker, &table);
> +}
> +
>  /* FADT */
>  static void build_fadt_rev6(GArray *table_data,
>                              BIOSLinker *linker,
> @@ -197,6 +270,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
>      acpi_add_table(table_offsets, tables_blob);
>      build_madt(tables_blob, tables->linker, s);
>  
> +    acpi_add_table(table_offsets, tables_blob);
> +    build_rhct(tables_blob, tables->linker, s);
> +
>      /* XSDT is pointed to by RSDP */
>      xsdt = tables_blob->len;
>      build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,



  reply	other threads:[~2023-02-24 12:56 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-24  8:36 [PATCH V4 0/8] Add basic ACPI support for risc-v virt Sunil V L
2023-02-24  8:36 ` [PATCH V4 1/8] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields Sunil V L
2023-02-24  8:36 ` [PATCH V4 2/8] hw/riscv/virt: Add a switch to disable ACPI Sunil V L
2023-02-24  8:36 ` [PATCH V4 3/8] hw/riscv/virt: Add memmap pointer to RiscVVirtState Sunil V L
2023-02-24  8:36 ` [PATCH V4 4/8] hw/riscv/virt: Enable basic ACPI infrastructure Sunil V L
2023-02-24  8:36 ` [PATCH V4 5/8] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT Sunil V L
2023-02-24 12:53   ` Igor Mammedov
2023-02-24 14:26     ` Sunil V L
2023-02-27 15:41       ` Igor Mammedov
2023-02-28  7:34         ` Sunil V L
2023-02-28 16:52           ` Igor Mammedov
2023-02-24  8:36 ` [PATCH V4 6/8] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table Sunil V L
2023-02-24 12:55   ` Igor Mammedov [this message]
2023-02-24  8:37 ` [PATCH V4 7/8] hw/riscv/virt.c: Initialize the ACPI tables Sunil V L
2023-02-24  8:37 ` [PATCH V4 8/8] MAINTAINERS: Add entry for RISC-V ACPI Sunil V L
2023-02-24 10:29   ` Andrew Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230224135545.0df4222f@imammedo.users.ipa.redhat.com \
    --to=imammedo@redhat.com \
    --cc=ajones@ventanamicro.com \
    --cc=alistair.francis@wdc.com \
    --cc=apatel@ventanamicro.com \
    --cc=atishp@rivosinc.com \
    --cc=bin.meng@windriver.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=sunilvl@ventanamicro.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).