From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, jcmvbkbc@gmail.com,
kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp,
gaosong@loongson.cn, jiaxun.yang@flygoat.com,
tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com,
edgar.iglesias@gmail.com
Subject: [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout
Date: Sun, 26 Feb 2023 19:41:46 -1000 [thread overview]
Message-ID: <20230227054233.390271-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org>
All uses are strictly read-only. Most of the obviously so,
as direct arguments to gen_helper_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 83 +++++++++++++++++++------------------
1 file changed, 42 insertions(+), 41 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 5d1fcc4b15..4d2a3349ec 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -884,7 +884,7 @@ static void gen_compute_eflags(DisasContext *s)
live = cc_op_live[s->cc_op] & ~USES_CC_SRCT;
dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2);
if (dead) {
- zero = tcg_const_tl(0);
+ zero = tcg_constant_tl(0);
if (dead & USES_CC_DST) {
dst = zero;
}
@@ -1412,7 +1412,7 @@ static void gen_helper_fp_arith_ST0_FT0(int op)
/* NOTE the exception in "r" op ordering */
static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
{
- TCGv_i32 tmp = tcg_const_i32(opreg);
+ TCGv_i32 tmp = tcg_constant_i32(opreg);
switch (op) {
case 0:
gen_helper_fadd_STN_ST0(cpu_env, tmp);
@@ -1439,7 +1439,7 @@ static void gen_exception(DisasContext *s, int trapno)
{
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno));
s->base.is_jmp = DISAS_NORETURN;
}
@@ -1633,7 +1633,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
/* Store the results into the CC variables. If we know that the
variable must be dead, store unconditionally. Otherwise we'll
need to not disrupt the current contents. */
- z_tl = tcg_const_tl(0);
+ z_tl = tcg_constant_tl(0);
if (cc_op_live[s->cc_op] & USES_CC_DST) {
tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl,
result, cpu_cc_dst);
@@ -1657,7 +1657,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
}
/* Conditionally store the CC_OP value. */
- z32 = tcg_const_i32(0);
+ z32 = tcg_constant_i32(0);
s32 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(s32, count);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
@@ -1813,7 +1813,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
exactly as we computed above. */
- t0 = tcg_const_i32(0);
+ t0 = tcg_constant_i32(0);
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, s->T1);
tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX);
@@ -2497,7 +2497,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
cc.reg = t0;
}
if (!cc.use_reg2) {
- cc.reg2 = tcg_const_tl(cc.imm);
+ cc.reg2 = tcg_constant_tl(cc.imm);
}
tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
@@ -2525,7 +2525,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg)
{
if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
- gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32);
+ gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware
@@ -4344,7 +4344,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) {
- TCGv imm = tcg_const_tl(x86_ldub_code(env, s));
+ TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
@@ -4503,7 +4503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0c: /* fldenv mem */
gen_helper_fldenv(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0d: /* fldcw mem */
@@ -4514,7 +4514,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x0e: /* fnstenv mem */
gen_helper_fstenv(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x0f: /* fnstcw mem */
@@ -4532,12 +4532,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break;
case 0x2c: /* frstor mem */
gen_helper_frstor(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2e: /* fnsave mem */
gen_helper_fsave(cpu_env, s->A0,
- tcg_const_i32(dflag - 1));
+ tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false;
break;
case 0x2f: /* fnstsw mem */
@@ -4587,12 +4587,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x08: /* fld sti */
gen_helper_fpush(cpu_env);
gen_helper_fmov_ST0_STN(cpu_env,
- tcg_const_i32((opreg + 1) & 7));
+ tcg_constant_i32((opreg + 1) & 7));
break;
case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */
- gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x0a: /* grp d9/2 */
switch (rm) {
@@ -4732,27 +4732,27 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
} else {
gen_helper_fmov_FT0_STN(cpu_env,
- tcg_const_i32(opreg));
+ tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1);
}
}
break;
case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
break;
case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x15: /* da/5 */
switch (rm) {
case 1: /* fucompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@@ -4786,7 +4786,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
@@ -4795,36 +4795,36 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
break;
case 0x28: /* ffree sti */
- gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2a: /* fst sti */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
break;
case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */
- gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x2c: /* fucom st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
break;
case 0x2d: /* fucomp st(i) */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
break;
case 0x33: /* de/3 */
switch (rm) {
case 1: /* fcompp */
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env);
@@ -4834,7 +4834,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
break;
case 0x38: /* ffreep sti, undocumented op */
- gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env);
break;
case 0x3c: /* df/4 */
@@ -4853,7 +4853,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@@ -4863,7 +4863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op;
}
gen_update_cc_op(s);
- gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS);
@@ -4886,7 +4886,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1);
- gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
+ gen_helper_fmov_ST0_STN(cpu_env,
+ tcg_constant_i32(opreg));
gen_set_label(l1);
}
break;
@@ -5092,8 +5093,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
- tcg_const_i32(val));
+ gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1),
+ tcg_constant_i32(val));
} else {
gen_stack_A0(s);
/* pop offset */
@@ -5120,7 +5121,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!check_vm86_iopl(s)) {
break;
}
- gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1));
} else {
gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s));
@@ -5509,7 +5510,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (val == 0) {
gen_exception(s, EXCP00_DIVZ);
} else {
- gen_helper_aam(cpu_env, tcg_const_i32(val));
+ gen_helper_aam(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
}
break;
@@ -5517,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (CODE64(s))
goto illegal_op;
val = x86_ldub_code(env, s);
- gen_helper_aad(cpu_env, tcg_const_i32(val));
+ gen_helper_aad(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB);
break;
/************************/
@@ -5698,7 +5699,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
- gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY;
}
break;
@@ -5717,7 +5718,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) {
gen_exception_gpf(s);
} else {
- gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1));
+ gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */
if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS);
@@ -5923,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1),
+ gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN;
@@ -5947,7 +5948,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1));
+ gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdb: /* VMSAVE */
@@ -5959,7 +5960,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
}
gen_update_cc_op(s);
gen_update_eip_cur(s);
- gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1));
+ gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1));
break;
case 0xdc: /* STGI */
--
2.34.1
next prev parent reply other threads:[~2023-02-27 8:29 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 5:41 [PATCH 00/70] tcg: Remove tcg_const_* Richard Henderson
2023-02-27 5:41 ` [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-06 13:54 ` Philippe Mathieu-Daudé
2023-03-06 13:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 02/70] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-02-27 5:41 ` [PATCH 03/70] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-06 14:00 ` Philippe Mathieu-Daudé
2023-03-06 19:20 ` Richard Henderson
2023-02-27 5:41 ` [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-06 13:58 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 05/70] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-02-27 5:41 ` [PATCH 06/70] target/arm: Improve trans_BFCI Richard Henderson
2023-02-27 5:41 ` [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-06 15:11 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 08/70] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-02-27 5:41 ` [PATCH 09/70] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-02-27 5:41 ` [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-06 15:15 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-06 15:22 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-06 13:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:49 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 14/70] target/cris: " Richard Henderson
2023-03-07 0:30 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 15/70] target/hexagon: Use tcg_constant_* for gen_constant_from_imm Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 17/70] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 22:00 ` Richard Henderson
2023-02-27 22:38 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-06 13:50 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 22/70] target/i386: Simplify POPF Richard Henderson
2023-02-27 9:04 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` Richard Henderson [this message]
2023-03-07 0:37 ` [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-02-27 5:41 ` [PATCH 25/70] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-06 14:14 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-06 23:53 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-07 0:03 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 23:59 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 29/70] target/microblaze: " Richard Henderson
2023-02-27 8:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 30/70] target/mips: Split out gen_lxl Richard Henderson
2023-03-06 13:31 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 31/70] target/mips: Split out gen_lxr Richard Henderson
2023-03-06 13:40 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-06 13:41 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 33/70] target/mips: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 13:46 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 34/70] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-06 15:08 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-06 14:16 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-02-27 5:42 ` [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-02-27 5:42 ` [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-02-27 5:42 ` [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-02-27 5:42 ` [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-02-27 5:42 ` [PATCH 45/70] target/riscv: Avoid tcg_const_* Richard Henderson
2023-02-27 9:05 ` Philippe Mathieu-Daudé
2023-03-06 13:53 ` liweiwei
2023-02-27 5:42 ` [PATCH 46/70] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-06 13:48 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-07 0:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-06 14:18 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 49/70] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:27 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 50/70] target/s390x: Split out gen_ri2 Richard Henderson
2023-02-27 9:09 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 51/70] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-07 0:23 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 53/70] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-06 15:36 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Richard Henderson
2023-03-01 17:02 ` Mark Cave-Ayland
2023-03-06 15:37 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-07 0:19 ` Philippe Mathieu-Daudé
2023-03-07 2:24 ` Richard Henderson
2023-03-07 10:20 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-06 15:38 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 58/70] target/tricore: Use min/max for saturate Richard Henderson
2023-02-27 5:53 ` Richard Henderson
2023-02-27 5:42 ` [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-06 15:39 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 60/70] target/tricore: Drop some temp initialization Richard Henderson
2023-03-06 15:25 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 61/70] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:10 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 62/70] target/xtensa: Tidy translate_bb Richard Henderson
2023-02-27 9:19 ` Max Filippov
2023-03-07 0:07 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 63/70] target/xtensa: Tidy translate_clamps Richard Henderson
2023-02-27 9:22 ` Max Filippov
2023-03-07 0:24 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r Richard Henderson
2023-02-27 9:23 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll Richard Henderson
2023-02-27 9:26 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 66/70] target/xtensa: Split constant in bit shift Richard Henderson
2023-02-27 9:27 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 67/70] target/xtensa: Avoid tcg_const_i32 Richard Henderson
2023-02-27 9:31 ` Max Filippov
2023-03-07 0:06 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-06 15:33 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 69/70] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-06 15:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 70/70] tcg: Drop tcg_const_* Richard Henderson
2023-03-06 15:30 ` Philippe Mathieu-Daudé
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