From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org,
qemu-s390x@nongnu.org, jcmvbkbc@gmail.com,
kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp,
gaosong@loongson.cn, jiaxun.yang@flygoat.com,
tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com,
edgar.iglesias@gmail.com
Subject: [PATCH 31/70] target/mips: Split out gen_lxr
Date: Sun, 26 Feb 2023 19:41:54 -1000 [thread overview]
Message-ID: <20230227054233.390271-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org>
Common subroutine for LDR and LWR.
Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/translate.c | 116 +++++++++++++-----------------------
1 file changed, 40 insertions(+), 76 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index f8ea7a54a3..5c5660da5a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2021,11 +2021,39 @@ static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr,
tcg_gen_or_tl(reg, t0, t1);
}
+/* LWR or LDR, depending on MemOp. */
+static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
+ int mem_idx, MemOp mop)
+{
+ int size = memop_size(mop);
+ int sizem1 = size - 1;
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ /*
+ * Do a byte access to possibly trigger a page
+ * fault with the unaligned address.
+ */
+ tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
+ tcg_gen_andi_tl(t1, addr, sizem1);
+ if (cpu_is_bigendian(ctx)) {
+ tcg_gen_xori_tl(t1, t1, sizem1);
+ }
+ tcg_gen_shli_tl(t1, t1, 3);
+ tcg_gen_andi_tl(t0, addr, ~sizem1);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop);
+ tcg_gen_shr_tl(t0, t0, t1);
+ tcg_gen_xori_tl(t1, t1, size * 8 - 1);
+ tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1);
+ tcg_gen_and_tl(t1, reg, t1);
+ tcg_gen_or_tl(reg, t0, t1);
+}
+
/* Load */
static void gen_ld(DisasContext *ctx, uint32_t opc,
int rt, int base, int offset)
{
- TCGv t0, t1, t2;
+ TCGv t0, t1;
int mem_idx = ctx->mem_idx;
if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
@@ -2066,26 +2094,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LDR:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 63);
- t2 = tcg_const_tl(0xfffffffffffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_gpr(t0, rt);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_const_tl(pc_relative_pc(ctx));
@@ -2153,27 +2164,10 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
/* fall through */
case OPC_LWR:
t1 = tcg_temp_new();
- /*
- * Do a byte access to possibly trigger a page
- * fault with the unaligned address.
- */
- tcg_gen_qemu_ld_tl(t1, t0, mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 31);
- t2 = tcg_const_tl(0xfffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_gpr(t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_ext32s_tl(t0, t0);
- gen_store_gpr(t0, rt);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL);
+ tcg_gen_ext32s_tl(t1, t1);
+ gen_store_gpr(t1, rt);
break;
case OPC_LLE:
mem_idx = MIPS_HFLAG_UM;
@@ -4150,7 +4144,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
static void gen_loongson_lswc2(DisasContext *ctx, int rt,
int rs, int rd)
{
- TCGv t0, t1, t2;
+ TCGv t0, t1;
TCGv_i32 fp0;
#if defined(TARGET_MIPS64)
int lsq_rt1 = ctx->opcode & 0x1f;
@@ -4225,29 +4219,12 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLWRC1:
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
- t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 3);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 3);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~3);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 31);
- t2 = tcg_const_tl(0xfffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
+ t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
-#if defined(TARGET_MIPS64)
- tcg_gen_extrl_i64_i32(fp0, t0);
-#else
- tcg_gen_ext32s_tl(fp0, t0);
-#endif
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
#if defined(TARGET_MIPS64)
@@ -4263,22 +4240,9 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
- tcg_gen_andi_tl(t1, t0, 7);
- if (cpu_is_bigendian(ctx)) {
- tcg_gen_xori_tl(t1, t1, 7);
- }
- tcg_gen_shli_tl(t1, t1, 3);
- tcg_gen_andi_tl(t0, t0, ~7);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
- tcg_gen_shr_tl(t0, t0, t1);
- tcg_gen_xori_tl(t1, t1, 63);
- t2 = tcg_const_tl(0xfffffffffffffffeull);
- tcg_gen_shl_tl(t2, t2, t1);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_and_tl(t1, t1, t2);
- tcg_gen_or_tl(t0, t0, t1);
- gen_store_fpr64(ctx, t0, rt);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_store_fpr64(ctx, t1, rt);
break;
#endif
default:
--
2.34.1
next prev parent reply other threads:[~2023-02-27 5:50 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-27 5:41 [PATCH 00/70] tcg: Remove tcg_const_* Richard Henderson
2023-02-27 5:41 ` [PATCH 01/70] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-06 13:54 ` Philippe Mathieu-Daudé
2023-03-06 13:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 02/70] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-02-27 5:41 ` [PATCH 03/70] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-06 14:00 ` Philippe Mathieu-Daudé
2023-03-06 19:20 ` Richard Henderson
2023-02-27 5:41 ` [PATCH 04/70] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-06 13:58 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 05/70] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-02-27 5:41 ` [PATCH 06/70] target/arm: Improve trans_BFCI Richard Henderson
2023-02-27 5:41 ` [PATCH 07/70] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} Richard Henderson
2023-03-06 15:11 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 08/70] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-02-27 5:41 ` [PATCH 09/70] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-02-27 5:41 ` [PATCH 10/70] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-06 15:15 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 11/70] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-06 15:22 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 12/70] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS Richard Henderson
2023-03-06 13:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 13/70] target/avr: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:49 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 14/70] target/cris: " Richard Henderson
2023-03-07 0:30 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 15/70] target/hexagon: Use tcg_constant_* for gen_constant_from_imm Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 16/70] target/hexagon/idef-parser: Use gen_tmp for LPCFG Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 17/70] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 18/70] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 19/70] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op Richard Henderson
2023-02-27 21:55 ` Taylor Simpson
2023-02-27 22:00 ` Richard Henderson
2023-02-27 22:38 ` Taylor Simpson
2023-02-27 5:41 ` [PATCH 20/70] target/hppa: Avoid tcg_const_i64 in trans_fid_f Richard Henderson
2023-03-06 13:50 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 21/70] target/hppa: Avoid use of tcg_const_i32 throughout Richard Henderson
2023-03-06 23:51 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 22/70] target/i386: Simplify POPF Richard Henderson
2023-02-27 9:04 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 23/70] target/i386: Avoid use of tcg_const_* throughout Richard Henderson
2023-03-07 0:37 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 24/70] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-02-27 5:41 ` [PATCH 25/70] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-06 14:14 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 26/70] target/m68k: Avoid tcg_const_i32 when modified Richard Henderson
2023-03-06 23:53 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 27/70] target/m68k: Avoid tcg_const_i32 in bfop_reg Richard Henderson
2023-03-07 0:03 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 28/70] target/m68k: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 23:59 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 29/70] target/microblaze: " Richard Henderson
2023-02-27 8:56 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 30/70] target/mips: Split out gen_lxl Richard Henderson
2023-03-06 13:31 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` Richard Henderson [this message]
2023-03-06 13:40 ` [PATCH 31/70] target/mips: Split out gen_lxr Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 32/70] target/mips: Avoid tcg_const_tl in gen_r6_ld Richard Henderson
2023-03-06 13:41 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 33/70] target/mips: Avoid tcg_const_* throughout Richard Henderson
2023-03-06 13:46 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 34/70] target/ppc: Split out gen_vx_vmul10 Richard Henderson
2023-03-06 15:08 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 35/70] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad Richard Henderson
2023-03-06 14:16 ` Philippe Mathieu-Daudé
2023-02-27 5:41 ` [PATCH 36/70] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-02-27 5:42 ` [PATCH 37/70] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 38/70] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-02-27 5:42 ` [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 40/70] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 41/70] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-02-27 5:42 ` [PATCH 42/70] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-02-27 5:42 ` [PATCH 43/70] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-02-27 5:42 ` [PATCH 44/70] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-02-27 5:42 ` [PATCH 45/70] target/riscv: Avoid tcg_const_* Richard Henderson
2023-02-27 9:05 ` Philippe Mathieu-Daudé
2023-03-06 13:53 ` liweiwei
2023-02-27 5:42 ` [PATCH 46/70] target/rx: Use tcg_gen_abs_i32 Richard Henderson
2023-03-06 13:48 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Richard Henderson
2023-03-07 0:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 48/70] target/rx: Avoid tcg_const_i32 when new temp needed Richard Henderson
2023-03-06 14:18 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 49/70] target/rx: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:27 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 50/70] target/s390x: Split out gen_ri2 Richard Henderson
2023-02-27 9:09 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 51/70] target/s390x: Avoid tcg_const_i64 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 52/70] target/sh4: Avoid tcg_const_i32 for TAS.B Richard Henderson
2023-03-07 0:23 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 53/70] target/sh4: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:21 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 54/70] tcg/sparc: Avoid tcg_const_tl in gen_edge Richard Henderson
2023-03-06 15:36 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Richard Henderson
2023-03-01 17:02 ` Mark Cave-Ayland
2023-03-06 15:37 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 56/70] target/tricore: Split t_n as constant from temp as variable Richard Henderson
2023-03-07 0:19 ` Philippe Mathieu-Daudé
2023-03-07 2:24 ` Richard Henderson
2023-03-07 10:20 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 57/70] target/tricore: Rename t_off10 and use tcg_constant_i32 Richard Henderson
2023-03-06 15:38 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 58/70] target/tricore: Use min/max for saturate Richard Henderson
2023-02-27 5:53 ` Richard Henderson
2023-02-27 5:42 ` [PATCH 59/70] target/tricore: Use setcondi instead of explicit allocation Richard Henderson
2023-03-06 15:39 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 60/70] target/tricore: Drop some temp initialization Richard Henderson
2023-03-06 15:25 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 61/70] target/tricore: Avoid tcg_const_i32 Richard Henderson
2023-03-07 0:10 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 62/70] target/xtensa: Tidy translate_bb Richard Henderson
2023-02-27 9:19 ` Max Filippov
2023-03-07 0:07 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 63/70] target/xtensa: Tidy translate_clamps Richard Henderson
2023-02-27 9:22 ` Max Filippov
2023-03-07 0:24 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 64/70] target/xtensa: Avoid tcg_const_i32 in translate_l32r Richard Henderson
2023-02-27 9:23 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 65/70] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll Richard Henderson
2023-02-27 9:26 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 66/70] target/xtensa: Split constant in bit shift Richard Henderson
2023-02-27 9:27 ` Max Filippov
2023-03-06 15:01 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 67/70] target/xtensa: Avoid tcg_const_i32 Richard Henderson
2023-02-27 9:31 ` Max Filippov
2023-03-07 0:06 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 68/70] tcg: Replace tcg_const_i64 in tcg-op.c Richard Henderson
2023-03-06 15:33 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 69/70] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-06 15:32 ` Philippe Mathieu-Daudé
2023-02-27 5:42 ` [PATCH 70/70] tcg: Drop tcg_const_* Richard Henderson
2023-03-06 15:30 ` Philippe Mathieu-Daudé
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